Could you explain a bit how your project is different from the one in the article? Why did they implement the SM83 in HDL when you already have such an implemen

Could you explain a bit how your project is different from the one in the article? Why did they implement the SM83 in HDL when you already have such an implementation? Also, I don't see any specific FPGA's mentioned, what sort of constraints do these projects have? Does it run on a 3$ one, or do you need something bigger /fancier? Edit: oh sorry didn't realize MIST is the device, it's an Altera Cyclone EP3C25