> MIPS, Itanium, SPARC and POWER all have weak memory models. This does not seem to hold for SPARC: according to > https://www.cl.cam.ac.uk/~pes20/weakmemory/

> MIPS, Itanium, SPARC and POWER all have weak memory models. This does not seem to hold for SPARC: according to > https://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tphols.pdf https://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.tpho... the (strong) memory models of x86 and SPARCv8 are very related: "We give two equivalent definitions of x86-TSO: an intuitive operational model based on local write buffers, and an axiomatic total store ordering model, similar to that of the SPARCv8." "Our x86-TSO axiomatic memory model is based on the SPARCv8 memory model specification [20, 21], but adapted to x86 and in the same terms as our ear- lier x86-CC model." "We have described x86-TSO, a memory model for x86 processors that does not suffer from the ambiguities, weaknesses, or unsoundnesses of earlier models. Its abstract-machine definition should be intuitive for programmers, and its equiva- lent axiomatic definition supports the memevents exhaustive search and permits an easy comparison with related models; the similarity with SPARCv8 suggests x86-TSO is strong enough to program above."