Heh, yes, sort of. Sure it's over 5 GHz. But their somewhere around 19 pipeline stages. So 19 parts of the chip, do 1/19th of the work of a single instructio

Heh, yes, sort of. Sure it's over 5 GHz. But their somewhere around 19 pipeline stages. So 19 parts of the chip, do 1/19th of the work of a single instruction, under ideal conditions (data is in registers, functional unit is available, etc). So something as simple as a=b+c gets split into 19 pieces. Sadly waiting on cache (l1, l2, and l3), main memory (4 32 bit channels approximately 100ns away), missed branch predictions, etc is fairly common. So delivered performance is much less than you'd think form a 6 way issue @ 6 GHz * 8 to 16 cores. Sadly we are still stuck at 128 bit wide memory, as a result even the most parallel of codes like cinebench go up by 50% when you double the number of cores.