3 ms·
I wonder how many erase/write cycles it can sustain. Interesting that the press release doesn't mention it. Previous generations had already descended as low as
by Lagged2Death 15y ago
I wonder how many erase/write cycles it can sustain. Interesting that the press release doesn't mention it. Previous generations had already descended as low as 3,000 cycles.
I realize wear-leveling makes it a non-issue in many applications, but I do wonder just how flimsy a memory we'll wind up settling for, too.
- cuu508 15y agoAnandTech says the new 20nm part is designed for the same 3K-5K as 25nm. http://www.anandtech.com/show/5193/intel-and-micron-imft-announce-worlds-first-128gb-20nm-mlc-nand http://www.anandtech.com/show/5193/intel-and-micron-imft-ann...