3 ms·

I don't think it would be. You'd have to detect them on the data bus and also differentiate between data and instruction accesses which I don't /think/ the Z80

I don't think it would be. You'd have to detect them on the data bus and also differentiate between data and instruction accesses which I don't /think/ the Z80 does, at least not easily.

brucehoult 4y ago
6502 has output pins that let you distinguish between instruction fetch, data read/write, and interrupt/reset vector fetch. So you can bank switch based on all that stuff. 6502 doesn't have a pin for "IO space" but you just pick your MMIO range e.g. 0xCnnn on the Apple ][ and a NAND gate on the 2 MSBs and a 3-input OR/NOR on the output and the next two bits gives you effectively the same signal. (or an OR gate on bits 12&13 plus a 3-input AND/NAND on bits 14&15 and the output). It was common to use 6522 VIA 8 bit output ports to bank switch one or two 4k ranges to allow each such 4k range to access 256*4k = 1 MB of RAM. You could use a 16x8 bit SRAM to do the same thing for the whole address space.
rep_lodsb 4y ago
It does have a pin for that (#M1, "machine cycle 1"). Zilog actually designed their peripheral chips to handle the RETI (return from interrupt) opcode specially. On the Z80 itself it does the same thing as a normal RET, but other chips can detect it on the bus and treat it as the signal that their interrupt handler is finished. I also recall reading about some hobby project to add a PC-relative addressing mode to the 8080 or Z80. A redundant opcode like "MOV A,A" would be used as a prefix, which caused the external hardware to add the program counter to the immediate operand of the following instruction. Can't find it right now.
- becurious 4y ago
  Using M1 plus the address lines was used to trap on certain addresses on expansion devices for the Spectrum such as Interface 1 or the +D. Then they’d use a line on the expansion bus to disable the standard ROM and substitute their own ROM / static RAM until some other trigger such as an OUT to a port would page the ROM back in. I guess it’s a short step to looking up memory addresses against a bitmap for validation. I couldn’t tell from the video if this is what he did. Cutting the addresses into pages would let you save or add more levels and I guess you could implement a TLB similarly.

I don't think it would be. You'd have to detect them on the data bus and also differentiate between data and instruction accesses which I don't /think/ the Z80 does, at least not easily.

brucehoult 4y ago

6502 has output pins that let you distinguish between instruction fetch, data read/write, and interrupt/reset vector fetch. So you can bank switch based on all that stuff. 6502 doesn't have a pin for "IO space" but you just pick your MMIO range e.g. 0xCnnn on the Apple ][ and a NAND gate on the 2 MSBs and a 3-input OR/NOR on the output and the next two bits gives you effectively the same signal. (or an OR gate on bits 12&13 plus a 3-input AND/NAND on bits 14&15 and the output). It was common to use 6522 VIA 8 bit output ports to bank switch one or two 4k ranges to allow each such 4k range to access 256*4k = 1 MB of RAM. You could use a 16x8 bit SRAM to do the same thing for the whole address space.

rep_lodsb 4y ago

It does have a pin for that (#M1, "machine cycle 1"). Zilog actually designed their peripheral chips to handle the RETI (return from interrupt) opcode specially. On the Z80 itself it does the same thing as a normal RET, but other chips can detect it on the bus and treat it as the signal that their interrupt handler is finished. I also recall reading about some hobby project to add a PC-relative addressing mode to the 8080 or Z80. A redundant opcode like "MOV A,A" would be used as a prefix, which caused the external hardware to add the program counter to the immediate operand of the following instruction. Can't find it right now.

becurious 4y ago
Using M1 plus the address lines was used to trap on certain addresses on expansion devices for the Spectrum such as Interface 1 or the +D. Then they’d use a line on the expansion bus to disable the standard ROM and substitute their own ROM / static RAM until some other trigger such as an OUT to a port would page the ROM back in. I guess it’s a short step to looking up memory addresses against a bitmap for validation. I couldn’t tell from the video if this is what he did. Cutting the addresses into pages would let you save or add more levels and I guess you could implement a TLB similarly.