One of my favorite technique for building a hardware RNG uses a cheapo FPGA circuit (something like this: https://www.aliexpress.com/item/32241350256.html?spm=a

One of my favorite technique for building a hardware RNG uses a cheapo FPGA circuit (something like this: https://www.aliexpress.com/item/32241350256.html?spm=a2g0o.productlist.0.0.47da52e2vIZCiT&algo_pvid=da8182e6-75f6-4f81-96b7-3c5ab357b0b8&algo_exp_id=da8182e6-75f6-4f81-96b7-3c5ab357b0b8-17&pdp_ext_f=%7B%22sku_id%22%3A%2256011206743%22%7D&pdp_npi=2%40dis%21EUR%2154.2%2137.95%21%21%214.67%21%21%40210318b916659522513785493eca33%2156011206743%21sea&curPageLogUid=HOTcKVGFGvph https://www.aliexpress.com/item/32241350256.html?spm=a2g0o.p...) with a bunch of free-running high-frequency oscillators called ring oscillators (basically loops of NOT gates, which have a lot of phase noise, especially if they run hot) that are sampled at constant frequency. The entropy isn't very "clean" (lots of auto-correlation), but it's unpredictable enough to seed a crypto hard RNG which can also be built into the FPGA and operate at very high speed. It's also an increasing PITA to convince synthesis tools to actually emit ring oscillators, which they consider to be a design bug (which they almost always are, except in this specific case), but it's still possible. [EDIT]: a quick search on github yields: https://github.com/stnolting/neoTRNG https://github.com/stnolting/neoTRNG https://github.com/Netnod/rosc_entropy https://github.com/Netnod/rosc_entropy