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Ask HN: Has a 4 core CPU with a "T" core layout been made?
If not, why not? It seems optimal when attempting to layout in 2D a 4 core CPU cluster with each of the cores directly connected to one another - above the top of the "T" would have a link to connect the end cores & cache fill in above & on the sides making a rectangle to cut. Compare Zen 1 & 2 with the cache in the center splitting the cores: https://i.ytimg.com/vi/NXprMIzv_uw/maxresdefault.jpg The same symmetric splitting with the i7-5960x & Zen 3 & 4 "octo-ring": https://cdn.wccftech.com/wp-content/uploads/2020/11/AMD-Ryzen-5000-Zen-3-Desktop-CPU_Vermeer_Die-Shot_1-scaled.jpg with the ring bringing the need for NUMA. The quad core I7-975 was linear https://www.guru3d.com/miraserver/images/2008/corei7/Nehalem_Die_callout.jpg Quad square configurations appear to have been used for Xeons: https://qph.cf2.quoracdn.net/main-qimg-6762cf8e384ca54f7d7640cadddd511f-pjlq & Athlons: https://static.techspot.com/articles-info/197/images/Image_02-j.webp, but not a "T". If latency being equal between the cores is the reason, then take out middle core & have equidistant tri-cores seesaw that could be linearly chained with the half core excess filled with cache on the ends, but again this does not appear to exist?
- db48x 4y agoDumb question. Remember that whatever shape you create has to be one that you can cut out of a wafer. The wafer is a foot across and has many, many tiny copies of your chip etched into the surface. You then use a saw to slice it up into individual devices. Concave shapes are therefore contraindicated.
- ffhhj 4y agoSaw or laser?
- duskwuff 4y agoCan be either, but saws are more common. The process is referred to as "wafer dicing".
- croo 4y agoNothing about processor core layout is easily understandable and to have the insight you just gave needs experience with the actual process. Therefore this question by its nature is not dumb. Don't preface answers with "dumb question". It kills curiosity.
- db48x 4y agoI would say that this is the easiest part of layout to understand; it is a gross physical requirement that anyone who has cut a piece of paper with scissors can reason about, rather than an electrical or signal processing problem.
- wmf 4y agoThe cores don't connect to each other; they connect to the shared cache. Existing layouts are probably near-optimal.
- downvotetruth 4y agoGiven that, it seems that hardware vendors have not wanted to invest in the scheduler / compiler to route outputs of one core to the inputs another when it would be useful such as lots of branching like speculative execution.
- wmf 4y agoYes, except for research projects like MIT RAW there aren't even instructions for cores to send data to each other. Cores only read/write/sync to memory (which is really cache) so data has to flow from a core to cache then to another core.