4 ms·
> One problem with the x86 pause instruction is the number of cycles spent paused has varied dramatically from one CPU to another. Some CPU models ignore it. On
by FartyMcFarter 4y ago
> One problem with the x86 pause instruction is the number of cycles spent paused has varied dramatically from one CPU to another. Some CPU models ignore it. On others it is very short, a few or ten cycles, and on some it is hundreds of cycles.
Here's a previous HN discussion about that (in particular Skylake CPUs greatly diverging from previous behaviour):
https://news.ycombinator.com/item?id=17336853 https://news.ycombinator.com/item?id=17336853
Original link:
https://aloiskraus.wordpress.com/2018/06/16/why-skylakex-cpus-are-sometimes-50-slower-how-intel-has-broken-existing-code/ https://aloiskraus.wordpress.com/2018/06/16/why-skylakex-cpu...
- jeffbee 4y agoThat is good info! The very latest Intel "client" parts have UMWAIT, which allows a thread to sleep until the TSC reaches a given value, or monitored range of addresses is stored. It's the best of both worlds: a thread can arm the monitor using the address of the lock, and sleep for a defined time. If the lock is released the thread will wake immediately. If not, the thread will wake at a predictable time. This feature isn't widespread and very few libraries on github use it.