The true/false on that page indicates whether the instruction has “MXCSR Configuration Dependent Timing.” This is separate from their sensitivity to the data-op

The true/false on that page indicates whether the instruction has “MXCSR Configuration Dependent Timing.” This is separate from their sensitivity to the data-operand independent timing MSR bit. My interpretation is that all of the instructions in that list require DOIT set for guarantees of data independent timing > a new model specific register (MSR) control enables data operand independent timing for the listed data operand independent timing instructions. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html https://www.intel.com/content/www/us/en/developer/articles/t...