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https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-... Pa

https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-... Page 12. > In the Turing generation, each of the four SM processing blocks (also called partitions) had two primary datapaths, but only one of the two could process FP32 operations. The other datapath was limited to integer operations. GA10X includes FP32 processing on both datapaths, doubling the peak processing rate for FP32 operations. One datapath in each partition consists of 16 FP32 CUDA Cores capable of executing 16 FP32 operations per clock. Another datapath consists of both 16 FP32 CUDA Cores and 16 INT32 Cores, and is capable of executing either 16 FP32 operations OR 16 INT32 operations per clock. As a result of this new design, each GA10x SM partition is capable of executing either 32 FP32 operations per clock, or 16 FP32 and 16 INT32 operations per clock. All four SM partitions combined can execute 128 FP32 operations per clock, which is double the FP32 rate of the Turing SM, or 64 FP32 and 64 INT32 operations per clock.

lostmsu 4y ago
As a non-involved, not sure I understand this quote correctly. Reads like Turing had 4 independent core equivalents, but 2 of them were incapable of FP; and Ampere has all 4 cores capable of doing either. But how are shaders scheduled to those cores? As a programmer, how do I see those cores and send code to run on them? Are there basic samples?
- dragontamer 4y ago
  An NVidia 'SM' is the closest thing to a CPU core. Each SM has multiple MIMD capabilities as it is, but I was focusing upon the dual-issue pipelines of FP32+integer instructions simultaneously. > As a programmer, how do I see those cores and send code to run on them? When the following assembly instructions are send to the GPU, they will execute simultaneously add.s32 r1, r2 add.f32 r3, r4 That is: the NVidia SM can process a floating point (f32) instruction simultaneously with integer (s32) instructions. ------ It sounds like you are getting confused by a lot of other features in the GPU SM. I dunno where exactly, but it's a complicated beast. All I really think I can say is to study up on GPU microarchitecture for more details, there is a lot going on here and it'd be too difficult for me to cover it all in just a few comments.

lostmsu 4y ago

As a non-involved, not sure I understand this quote correctly. Reads like Turing had 4 independent core equivalents, but 2 of them were incapable of FP; and Ampere has all 4 cores capable of doing either. But how are shaders scheduled to those cores? As a programmer, how do I see those cores and send code to run on them? Are there basic samples?

dragontamer 4y ago
An NVidia 'SM' is the closest thing to a CPU core. Each SM has multiple MIMD capabilities as it is, but I was focusing upon the dual-issue pipelines of FP32+integer instructions simultaneously. > As a programmer, how do I see those cores and send code to run on them? When the following assembly instructions are send to the GPU, they will execute simultaneously add.s32 r1, r2 add.f32 r3, r4 That is: the NVidia SM can process a floating point (f32) instruction simultaneously with integer (s32) instructions. ------ It sounds like you are getting confused by a lot of other features in the GPU SM. I dunno where exactly, but it's a complicated beast. All I really think I can say is to study up on GPU microarchitecture for more details, there is a lot going on here and it'd be too difficult for me to cover it all in just a few comments.