The eDP spec specifies a set of timings that should be waited on in between certain actions. There is a minimum timing between power cycling the panel, between

The eDP spec specifies a set of timings that should be waited on in between certain actions. There is a minimum timing between power cycling the panel, between powering-on and sending auxiliary messages, between setting modes, etc. Those timings are read from the a BIOS table called the VBT (among other conflicting sources sometimes), and the patch in question reworks VBT code. In practice not respecting these timings is kinda like toggling your ceiling lights on/off repeatedly. I bet your parents used to tell you the house could be set on fire if you did that, but you did it anyway and nothing ever happened. I think it's unlikely somebody will actually be able to damage their panels with that bug. But hey I'm pulling this guess out of my ass so don't quote me on that. But that can result in the panel failing to turn on and giving you a black or flickering screen. In fact, at least a few years ago when I looked at this, the Intel driver was very conservative regarding those numbers because a long time ago in a galaxy far away the VBT values for some laptop models were bogus, so as a result nearly everybody had timeouts longer than what they needed to. There's a chance that even with a bogus VBT you're waiting more than you should for your panel. But that doesn't really affect real people very much, it's only really a significant problem if you're testing Display code and doing thousands of modesets per minute. Unless you're getting black screens, of course.