3 ms·

yeah you see I think that's the riscy-ish thing of it all, and why I nominated it: having bits in the instructions wired directly to gates in the ALU without an

yeah you see I think that's the riscy-ish thing of it all, and why I nominated it: having bits in the instructions wired directly to gates in the ALU without any decode is RISC at its essence

brucehoult 4y ago
In some ways. Maybe it's more like a short VLIW :-) Either way, it's not conducive to having an Instruction Set Architecture with varying implementations.
- Taniwha 4y ago
  I think that's fair - but then jump delay slots used in a lot of early riscs, including the 801 are very VLIWy too (the one I worked on could have up to 3 instructions in a delay slot)
  - kragen 4y ago
    I'd never thought of it that way!