2 ms·

>Zero-wait-state memory was still a thing in workstations up to the 90s; there was no latency of loads from memory. That is not correct. Even PCs started to g

>Zero-wait-state memory was still a thing in workstations up to the 90s; there was no latency of loads from memory. That is not correct. Even PCs started to get caches in around 1985-1987. In 1985 the 80386 supported an optional external SRAM cache. In 1984 the 68020 had a 256 byte instruction cache. 1987's 68030 added a 256 byte data cache. Apple's 1989 Mac IIci added an optional 16k external cache to the 68030, which was actually bought by everyone I knew who had one, as it made a considerable speed difference. The 80486 (1989) and 68040 (1990) had 8k unified and 4k+4k I&D caches respectively. RISC workstations of course had caches before Macs&PCs did.

kragen 4y ago
I appreciate the corrections, and I think I went through most of these in my earlier comment https://news.ycombinator.com/item?id=33059665 https://news.ycombinator.com/item?id=33059665 but I had the impression that the reason for the caches was mostly to reduce the required memory bandwidth. This is of course a stronger reason for an icache than a dcache. As you can see in that thread, I haven't been able to find any shipping RISC CPUs that had a cache before the 68020 in 01984. In particular I haven't found evidence that the ROMP had a cache, even though it was derived from the split-cache 801. Maybe you know of some? I must have been wrong about the latency of DRAM in the late 01980s. Even today I suppose single-banked DRAM usually tops out at 10 MHz for random accesses?
- adrian_b 4y ago
  Intel 8086/8088 had slow memory access, an access cycle was at least 4 clock cycles and it was easy to find DRAM that would not need wait cycles, e.g. for an IBM PC/XT. Intel 80286 has completely changed the memory bus and it could complete a memory access in only 2 clock cycles, and inside those 2 clock cycles there was little time from when the address was available until the data had to be returned by the memory for no wait states. Even for the first model of IBM PC/AT, with a very slow 80286 @ 6 MHz (despite the fact that 80286 had been officially launched with clock frequencies starting at 8 MHz), it would have been difficult to find fast enough DRAM to avoid the wait states. The desire of minimizing or avoiding the wait states could have been the reason for the very low clock frequency, unless Intel had manufacturing problems and could not supply enough 80286 @ 8 MHz or @ 12 MHz. For the later faster 80286 models and for the 80386, which started in 1985 at 12 MHz and 16 MHz, it was pretty much impossible to find DRAM that would allow a 2-clock-cycle memory access cycle. The majority of the PC/AT clones with 80286 or 80386 used one or more wait states for the DRAM and all the high-end PC/AT clones with 80386DX CPUs had external cache memories made with fast SRAM, e.g. of 32 kbyte or 64 kbyte size, which was the only memory that could be used without wait states. Even after Intel included the L1 cache in 486 and Pentium, all the decent motherboards had an external L2 cache with SRAM. The external caches have disappeared only after 2000, when the later models of Intel Pentium III and AMD Athlon have included on the chip also the L2 cache memory.

kragen 4y ago

I appreciate the corrections, and I think I went through most of these in my earlier comment https://news.ycombinator.com/item?id=33059665 https://news.ycombinator.com/item?id=33059665 but I had the impression that the reason for the caches was mostly to reduce the required memory bandwidth. This is of course a stronger reason for an icache than a dcache. As you can see in that thread, I haven't been able to find any shipping RISC CPUs that had a cache before the 68020 in 01984. In particular I haven't found evidence that the ROMP had a cache, even though it was derived from the split-cache 801. Maybe you know of some? I must have been wrong about the latency of DRAM in the late 01980s. Even today I suppose single-banked DRAM usually tops out at 10 MHz for random accesses?

adrian_b 4y ago
Intel 8086/8088 had slow memory access, an access cycle was at least 4 clock cycles and it was easy to find DRAM that would not need wait cycles, e.g. for an IBM PC/XT. Intel 80286 has completely changed the memory bus and it could complete a memory access in only 2 clock cycles, and inside those 2 clock cycles there was little time from when the address was available until the data had to be returned by the memory for no wait states. Even for the first model of IBM PC/AT, with a very slow 80286 @ 6 MHz (despite the fact that 80286 had been officially launched with clock frequencies starting at 8 MHz), it would have been difficult to find fast enough DRAM to avoid the wait states. The desire of minimizing or avoiding the wait states could have been the reason for the very low clock frequency, unless Intel had manufacturing problems and could not supply enough 80286 @ 8 MHz or @ 12 MHz. For the later faster 80286 models and for the 80386, which started in 1985 at 12 MHz and 16 MHz, it was pretty much impossible to find DRAM that would allow a 2-clock-cycle memory access cycle. The majority of the PC/AT clones with 80286 or 80386 used one or more wait states for the DRAM and all the high-end PC/AT clones with 80386DX CPUs had external cache memories made with fast SRAM, e.g. of 32 kbyte or 64 kbyte size, which was the only memory that could be used without wait states. Even after Intel included the L1 cache in 486 and Pentium, all the decent motherboards had an external L2 cache with SRAM. The external caches have disappeared only after 2000, when the later models of Intel Pentium III and AMD Athlon have included on the chip also the L2 cache memory.