4 ms·

I'd include the PDP-8 and successors/cloners like the DG NOVA

kragen 4y ago
The PDP-8 is certainly simple, but it has microcode, doesn't have pipelined execution, never approaches one instruction per clock, has memory operands to virtually every instruction (including an indirection bit, a mortal sin in RISC), and has a tiny register set. You could say its zero page is like a "large orthogonal general-purpose register set" but ⓐ all your ALU instructions have to involve a register which isn't in that set (the single accumulator) and ⓑ the current PC page is is just as accessible as the zero page. All it has in common with RISC is the fixed-width instruction set and a (very) small number of instruction formats. So I would say the PDP-8 is the opposite extreme from RISC. If you like the PDP-8 you should check out the 32-bit version: https://github.com/johnwcowan/pdp8x https://github.com/johnwcowan/pdp8x The NOVA is maybe a little more plausible, since it at least has a load-store architecture and four accumulators instead of one, but it still doesn't feel very RISCy to me. I mean it's maybe less RISCy than the 80386?
- kragen 4y ago
  Correction: although the PDP-8 has "microcoded" instructions, the "microcode" is actually in the instruction. There isn't a microcode store that runs a little program to implement each instruction, as there is on, for example, the 6502.
  - Taniwha 4y ago
    yeah you see I think that's the riscy-ish thing of it all, and why I nominated it: having bits in the instructions wired directly to gates in the ALU without any decode is RISC at its essence
    - brucehoult 4y ago
      In some ways. Maybe it's more like a short VLIW :-) Either way, it's not conducive to having an Instruction Set Architecture with varying implementations.
      - Taniwha 4y ago
        I think that's fair - but then jump delay slots used in a lot of early riscs, including the 801 are very VLIWy too (the one I worked on could have up to 3 instructions in a delay slot)
        kragen 4y ago
        I'd never thought of it that way!

The PDP-8 is certainly simple, but it has microcode, doesn't have pipelined execution, never approaches one instruction per clock, has memory operands to virtually every instruction (including an indirection bit, a mortal sin in RISC), and has a tiny register set. You could say its zero page is like a "large orthogonal general-purpose register set" but ⓐ all your ALU instructions have to involve a register which isn't in that set (the single accumulator) and ⓑ the current PC page is is just as accessible as the zero page. All it has in common with RISC is the fixed-width instruction set and a (very) small number of instruction formats. So I would say the PDP-8 is the opposite extreme from RISC. If you like the PDP-8 you should check out the 32-bit version: https://github.com/johnwcowan/pdp8x https://github.com/johnwcowan/pdp8x The NOVA is maybe a little more plausible, since it at least has a load-store architecture and four accumulators instead of one, but it still doesn't feel very RISCy to me. I mean it's maybe less RISCy than the 80386?

kragen 4y ago
Correction: although the PDP-8 has "microcoded" instructions, the "microcode" is actually in the instruction. There isn't a microcode store that runs a little program to implement each instruction, as there is on, for example, the 6502.
- Taniwha 4y ago
  yeah you see I think that's the riscy-ish thing of it all, and why I nominated it: having bits in the instructions wired directly to gates in the ALU without any decode is RISC at its essence
  - brucehoult 4y ago
    In some ways. Maybe it's more like a short VLIW :-) Either way, it's not conducive to having an Instruction Set Architecture with varying implementations.
    - Taniwha 4y ago
      I think that's fair - but then jump delay slots used in a lot of early riscs, including the 801 are very VLIWy too (the one I worked on could have up to 3 instructions in a delay slot)
      - kragen 4y ago
        I'd never thought of it that way!