5 ms·

Multiple FPGAs on a Board

2 points by daly 4y ago

(ref: https://news.ycombinator.com/item?id=33032036) I'm looking for multiple FPGAs on a single board. The prior request got only a single response, the HTG-847 ( https://www.xilinx.com/products/boards-and-kits/1-fb2a7b.html ). However, the board is too expensive and could not be programmed by open source software. The ideal case is a single board with 4 chips (and a scalable design to other powers of 2). The goal is a board to experiment with various software / hardware architectures that is fully programmable. The only solution seems to be to create such a board. At the moment I'm looking the Artix 7 100T chip (https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet). It can be programmed with open source software. Suggestions, comments, and snide remarks are most welcome.

detaro 4y ago
Any board like that would probably be extremely niche and thus expensive, since there is no obvious "correct" way how it should be done for a general case. I'd look into finding a board with little extras and wiring up (potentially through a simple backplane) multiple ones of those. Or go for one big FPGA and just run different topologies between components inside that.
- daly 4y ago
  I already have experimented with multiple FPGAs and a big FPGA. I'm looking into ideas like "push learning into the fingers". For example, when you learn to type you gradually move a computed action (finding the right key) into a twitch reaction (moving it into the fingers). One way to do this is to dump the state machine from an FPGA, add a new state that captures the action, and reloading the FPGA. There are lots of issues to study and puzzles to solve. For example, if one FPGA is using a neural net to train, can a "piece" of that neural net be "extracted" into a state machine state? I'm experimenting with the interaction / combination of neural nets and state machines. How can a "subset of neural net learning" become an independent state? I've not found any research on the intersection of state machines and neural nets, nor any research on the idea of "moving behavior into the fingers". I haven't found any research on self-modifying FPGAs, nor any research on self-modifying FPGAs using genetic programming. I want to be able to A/B test one FPGA output against another. A single big FPGA requires proprietary software that can't handle the dump/reload idea. Multiple FPGAs have very limited pathways for interaction. Neither seem to be the best medium.

2 points by daly 4y ago

detaro 4y ago

Any board like that would probably be extremely niche and thus expensive, since there is no obvious "correct" way how it should be done for a general case. I'd look into finding a board with little extras and wiring up (potentially through a simple backplane) multiple ones of those. Or go for one big FPGA and just run different topologies between components inside that.

daly 4y ago
I already have experimented with multiple FPGAs and a big FPGA. I'm looking into ideas like "push learning into the fingers". For example, when you learn to type you gradually move a computed action (finding the right key) into a twitch reaction (moving it into the fingers). One way to do this is to dump the state machine from an FPGA, add a new state that captures the action, and reloading the FPGA. There are lots of issues to study and puzzles to solve. For example, if one FPGA is using a neural net to train, can a "piece" of that neural net be "extracted" into a state machine state? I'm experimenting with the interaction / combination of neural nets and state machines. How can a "subset of neural net learning" become an independent state? I've not found any research on the intersection of state machines and neural nets, nor any research on the idea of "moving behavior into the fingers". I haven't found any research on self-modifying FPGAs, nor any research on self-modifying FPGAs using genetic programming. I want to be able to A/B test one FPGA output against another. A single big FPGA requires proprietary software that can't handle the dump/reload idea. Multiple FPGAs have very limited pathways for interaction. Neither seem to be the best medium.