4 ms·

Maybe. If I remember well, Apple ARM M1 can decode up to 8 instruction at the same time, is-there any RISC-V CPU with the C extension which is able to decode 8

• snvzz 4y ago
  >is-there any RISC-V CPU with the C extension which is able to decode 8 instructions? Sure, there's Ascalon[0], 8-decode 10-issue, by Jim Keller's team at Tenstorrent. It isn't in the market yet, but is bound to be among the first RISC-V chips targeting very high performance. Note that, at that size (8-decode implies lots of execution units, a relatively large design*), the negligible overhead of C extension is invisible. There's only gains to be had. C extension decode overhead would only apply in the comically impractical scenario of a core that has neither L1 Cache nor any ROM in the chip. Otherwise, it is a net win. And such a specialized chip would simply not implement C. 0. https://youtu.be/yHrdEcsr9V0?t=346 https://youtu.be/yHrdEcsr9V0?t=346 (*: 8-wide decode being small is just Jim Keller's idea of a joke)