Posits have a variable size mantissa, and the largest mantissa for a given bit size (eg, 32 bit floats) is larger than the mantissa in the corresponding IEEE fl

Posits have a variable size mantissa, and the largest mantissa for a given bit size (eg, 32 bit floats) is larger than the mantissa in the corresponding IEEE float. For example, in a 32 bit float, the IEEE mantissa is 23 bits, while the maximum size Posit mantissa is 27 bits. So a Posit FPU requires more mantissa bits than the IEEE FPU of the same bitsize, and this is why the Posit FPU will have a larger silicon footprint. IEEE needs a bit more silicon to manage all the special cases of IEEE logic, but apparently this is less than the extra transistors required for the Posit mantissa. (The extra cost for the mantissa is related to the better accuracy reported for posits.) Gustafson's paper is old, and doesn't reflect the language of the recent Posit standard. He may have had a different silicon implementation in mind than what has been implemented. Gustafson says there is no NaN. But in the Posit standard, there is a single NaN-like value called NaR (Not a Real). In IEEE, 0/0 is NaN, while in Posit, 0/0 is NaR. The rules for NaN and NaR are different, so they have different names.