3 ms·

> Is it? I've heard this before but I'm having trouble seeing this statement justified. > Wikipedia shows the cost of computing over time and, as far as I can

> Is it? I've heard this before but I'm having trouble seeing this statement justified. > Wikipedia shows the cost of computing over time and, as far as I can tell, is almost exactly a halving of cost every 1.5 years [0]. Not moore's law (stacking transistors will likely help for a whiles yet), but you can pretty easily chart the progress towards the landauer limit and see the plateau in the current paradigm coming (by my count about 3-5 orders of magnitude in energy efficiency of classical computing is the asymptote before you start throwing away 99% of the cpu and replacing it with 100 special case gated ones if you want more efficiency). As you approach the limit then the tricks that CPUs pull become a larger and larger portion of your energy, and progress is made by simplifying things and making each task more specialised as the article talks about. For more transistors on a plane they're hitting some hard limits. Currently gate pitch is ~30nm. Maybe at max a factor of 10 improvement is available for things made of atoms pushing around electrons. This gives 100x the transistor density as the end state of an industry that is already spending exponentially more on developing each generation of fab At some point stacking layers will have a greater than logarithmic cost per layer, and then storage will be done too. Very roughly maxing out at a 1 exabyte microsd card. The predictions I'm making here can be considered to have a somewhat hard time limit as the remaining 6-12 accessible doublings in each category must happen at a pace such that it is obviously true or false by 2040. eg. If there are 3 doublings in general purpose single threaded CPU power efficiency between 2035 and 2040 or gate pitch of transistors hits 1nm or storage costs are halving faster than once every 18mo in 2040 I am definitely wrong. Reversible computing is not bound by the ~5 OOM efficiency increase, but will be a substantially different paradigm (you can't delete anything for example).

memetomancer 4y ago
Perhaps you are unaware of the angstrom scale process nodes on the semiconductor roadmaps? i.e., IMEC, TSMC and Intel all aggressively pursuing "20A" at the moment with an eye toward a new generation of sub-1n production. This isn't just some arbitrary guesswork on a blog, it's practical planning by the major suppliers. Check it out.
- jcranmer 4y ago
  Note that the size label of process nodes is almost completely uncorrelated to actual feature size. GP makes the comment that the existing ~5-7nm nodes are actually running at ~30nm gate pitch.
- Schroedingersat 4y ago
  Please don't be condescending and wrong at the same time. The quantum tunnelling limit didn't mysteriously go away because the marketing department decided to name things based on the thickness of one particular feature. Nor do the laws of physics change when you bury your transistor in dialectric (the wavelength does, but that only works once). Node name just barely correlates with minimum feature size (how thin can a line be drawn). That's starting to break down (hence intel 7 and 2N and so on) but that's not the limit I'm speaking of. The "2nm" nodes wind up with functional units about 30nm from center to center. Compare to the 22nm node which was almost precisely 44nm center to center for a dram cell. In density terms there's maybe a factor of ~20 between 22nm and 2nm processes, so functionally the 2nm node can make things which are about a fifth the linear dimension. Gate pitch has a fairly hard limit based on voltage and electron wavelength. You're never going to put another transistor within about 2nm of a first one and have them both work. Hence the roughly order of magnitude in linear dimension past current.
  - memetomancer 4y ago
    I wasn't being condescending, and I am objectively not 'wrong'. I merely urged you to gather information you may not be familiar with. Particularly IMECs roadmap. I will point out that you instantly went into condescending mode after complaining about my imagined condescension. I assure you, I'm well aware of what a process node implies about measurement of larger features. I'm also aware of the promising approaches coming down the pike. I'm _also_ aware of the decades-old Internet tradition of people posting about the hard physical limits and immediate death of Moore's law, even as the limits are overcome year after year. I am glad that you have a handle on the problems we face here, but please try to keep in mind that these challenges are a beginning, not an end.

memetomancer 4y ago

Perhaps you are unaware of the angstrom scale process nodes on the semiconductor roadmaps? i.e., IMEC, TSMC and Intel all aggressively pursuing "20A" at the moment with an eye toward a new generation of sub-1n production. This isn't just some arbitrary guesswork on a blog, it's practical planning by the major suppliers. Check it out.

jcranmer 4y ago
Note that the size label of process nodes is almost completely uncorrelated to actual feature size. GP makes the comment that the existing ~5-7nm nodes are actually running at ~30nm gate pitch.
Schroedingersat 4y ago
Please don't be condescending and wrong at the same time. The quantum tunnelling limit didn't mysteriously go away because the marketing department decided to name things based on the thickness of one particular feature. Nor do the laws of physics change when you bury your transistor in dialectric (the wavelength does, but that only works once). Node name just barely correlates with minimum feature size (how thin can a line be drawn). That's starting to break down (hence intel 7 and 2N and so on) but that's not the limit I'm speaking of. The "2nm" nodes wind up with functional units about 30nm from center to center. Compare to the 22nm node which was almost precisely 44nm center to center for a dram cell. In density terms there's maybe a factor of ~20 between 22nm and 2nm processes, so functionally the 2nm node can make things which are about a fifth the linear dimension. Gate pitch has a fairly hard limit based on voltage and electron wavelength. You're never going to put another transistor within about 2nm of a first one and have them both work. Hence the roughly order of magnitude in linear dimension past current.
- memetomancer 4y ago
  I wasn't being condescending, and I am objectively not 'wrong'. I merely urged you to gather information you may not be familiar with. Particularly IMECs roadmap. I will point out that you instantly went into condescending mode after complaining about my imagined condescension. I assure you, I'm well aware of what a process node implies about measurement of larger features. I'm also aware of the promising approaches coming down the pike. I'm _also_ aware of the decades-old Internet tradition of people posting about the hard physical limits and immediate death of Moore's law, even as the limits are overcome year after year. I am glad that you have a handle on the problems we face here, but please try to keep in mind that these challenges are a beginning, not an end.