4 ms·

I hadn't heard the term chiplet before, thank you! When I got out of school in the late 90s, system-on-chip (SoC) was a pipe dream. It has issues because memory

I hadn't heard the term chiplet before, thank you! When I got out of school in the late 90s, system-on-chip (SoC) was a pipe dream. It has issues because memory might have different requirements than CPU, so it's hard to put all of the components on a single die. I always thought the situation was frankly pretty silly, because I didn't want one big die anyway. I wanted a scaleable grid of chips like the 3D processor from the Terminator 2 movie. It took over 20 years, but maybe we'll have a chance to get something like that with an open source RISC-V. Maybe an array of matchhead-size CPUs at 1 GHz costing $1 each that could be scaled to hundreds or thousands of cores with content-addressable memory for automatic caching and data locality. Then it could be treated as a single processor with access to a one large shared memory space and we could drop the (contrived) distinction between CPU/GPU/TPU/etc and get back to simple desktop computing rather than dealing with the friction of vertex buffers. My guess is that Nvidia doesn't want any of that to happen, so works to maintain its dominance in single-die solutions.

paulmd 4y ago
"match-head sized chiplets" sort of falls into the chiplet mythos I think. Chiplets aren't magic, they actually increase power usage vs an equivalent monolithic chip, data movement is expensive and the more data you move the more expensive it is. People just think chiplets are efficient because AMD made a huge node leap (GF 12nm to TSMC 7nm is like, more than a full node, probably at least 1.5 if not 2) at the same time, but chiplets have their own costs. The smaller you split the chiplets, the more data is moving around. And the more power you'll burn. It's not desirable to go super small, you want some reasonably-sized chiplet to minimize data movement. Even if you keep the chiplets "medium-sized" and just use a lot of them... there is still some new asymptotic efficiency limit where data movement power starts to overwhelm your savings from clocking the chips lower/etc. And there's copper-copper bonding to try and fix that, but that makes thermal density even worse (and boy is Zen4 hot already... 95C under any load). Like everything else, it's just kicking the can down the road, it doesn't solve all the problems forever.

paulmd 4y ago

"match-head sized chiplets" sort of falls into the chiplet mythos I think. Chiplets aren't magic, they actually increase power usage vs an equivalent monolithic chip, data movement is expensive and the more data you move the more expensive it is. People just think chiplets are efficient because AMD made a huge node leap (GF 12nm to TSMC 7nm is like, more than a full node, probably at least 1.5 if not 2) at the same time, but chiplets have their own costs. The smaller you split the chiplets, the more data is moving around. And the more power you'll burn. It's not desirable to go super small, you want some reasonably-sized chiplet to minimize data movement. Even if you keep the chiplets "medium-sized" and just use a lot of them... there is still some new asymptotic efficiency limit where data movement power starts to overwhelm your savings from clocking the chips lower/etc. And there's copper-copper bonding to try and fix that, but that makes thermal density even worse (and boy is Zen4 hot already... 95C under any load). Like everything else, it's just kicking the can down the road, it doesn't solve all the problems forever.