3 ms·
It's that it's a pain for precise exceptions. Handling how you get a page fault for ldm/stm and then restart them once the relevant page is loaded is non trivi
by monocasa 4y ago
It's that it's a pain for precise exceptions. Handling how you get a page fault for ldm/stm and then restart them once the relevant page is loaded is non trivial.
- fulafel 4y agoDon't they still have to handle that for the remaining "load 2" instructions?
- monocasa 4y agoNo, a single 128bit load/store even if it addresses two registers is way easier to handle than dumping a variable amount of your whole register file in a single instruction. That's why the ARM1 had a microcode engine for LDM/STM despite having 'RISC' as the center letter in it's initialism.