4 ms·
this (and the barrel shifter being available in all instructions) was at least partially due to the limitation mentioned in the article that the processor had n
by rrss 4y ago
this (and the barrel shifter being available in all instructions) was at least partially due to the limitation mentioned in the article that the processor had no data or instruction cache. If single instructions could have these extra capabilities, the processor could do more work between stalling waiting to read the next instruction from memory.