4 ms·
But you have that handshake anyway now, between the CPU and the memory controller, effectively at least, don't you?
by buescher 4y ago
But you have that handshake anyway now, between the CPU and the memory controller, effectively at least, don't you?
- wmf 4y agoNo, you don't. AFAIK DRAM chips just sit idle until the memory controller gives them a command and then they perform the command immediately.
- buescher 4y agoBut the memory controller still has to refresh them. So at some point you have to negotiate a wait state, don't you?
- mistrial9 4y agothey design for a very, very small edge on the signal state transition.. so yes technically but its meant to be negligible, I believe.. (not a hardware designer but I have looked over the shoulder a few times)
- londons_explore 4y agoYes - everything 'upstrram' of the memory controller has variable latency, partly because of the chance that a read or write request has to wait for a refreshing operation.
- mumumu 4y agoThey can sleep, but waking up has a large latency.