3 ms·
I always wondered why DRAM didn't just, after some Moore's law point, have refresh control built in. There's probably a reason I've forgotten about. Nice to s
by buescher 4y ago
I always wondered why DRAM didn't just, after some Moore's law point, have refresh control built in. There's probably a reason I've forgotten about. Nice to see someone at least thinking about it.
- wmf 4y agoYou'd have to introduce a handshake between the DRAM and the memory controller because some internal operation might already be in progress when the memory controller sends a command. You'd probably also want to sync all the DRAM chips on a DIMM so the memory controller doesn't have to deal with commands being partially blocked.
- buescher 4y agoBut you have that handshake anyway now, between the CPU and the memory controller, effectively at least, don't you?
- wmf 4y agoNo, you don't. AFAIK DRAM chips just sit idle until the memory controller gives them a command and then they perform the command immediately.
- buescher 4y agoBut the memory controller still has to refresh them. So at some point you have to negotiate a wait state, don't you?
- mistrial9 4y agothey design for a very, very small edge on the signal state transition.. so yes technically but its meant to be negligible, I believe.. (not a hardware designer but I have looked over the shoulder a few times)
- londons_explore 4y agoYes - everything 'upstrram' of the memory controller has variable latency, partly because of the chance that a read or write request has to wait for a refreshing operation.
- mumumu 4y agoThey can sleep, but waking up has a large latency.
- mumumu 4y agoI has been a while since I wrote a DRAM controller. But it's all about managing latencies. To achieve maximum throughput the controller needs to issue the operation in a specific order, different for each workload. DRAM have self refresh mode.