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> new low-cost DRAM architecture Provides no evidence that putting more logic into the DRAM will somehow be cheaper

wtallis 4y ago
The DRAM chips don't actually have to be cheaper. They just need to enable the system as a whole to be more cost effective. If putting a bit more logic in the DRAM makes it significantly cheaper and quicker to design and validate a processor's memory controller, and enables better performance and power efficiency from the memory, then it's very likely a net win even if the marginal cost of DRAM chips went up slightly.
- Lramseyer 4y ago
  While you're correct that overall system cost is what matters, most functionality is offloaded to the controller because a single controller often controls multiple DRAM chips (Like the chips all share a CA bus[1]) So it's cheaper to put the functionality in the controller. With that being said, it gets a bit nuanced, because as we make faster and faster DRAMs, we need more complicated input/output electronics (Phy and ECC.) GDDR actually has self refresh as part of the spec and even allows DRAM vendors to put a PLL inside so you can run a half rate clock, which technically makes it "Quadruple Data Rate" instead of "Double Data Rate." But usually with GDDR, you're running one controller per DRAM. Clamshell mode is not super common in my experience. [1] I'm not super well versed on DDR4 and all of its configurations. So someone who is can elaborate if they would like.
londons_explore 4y ago
Putting a controller in the dram allows that controller to detect bad memory cells and repair data (ecc-like) or re-map data to other addresses. Both of those things would be possible while implementing the regular 'dumb' dram interface, but any error detection or remapping would have to operate within the latency budget of the module, since the latency is fixed. Typically that means not much remapping can be done, and ram yields have to be really good. With this change, ram becomes robust to far more silicon defects like nand flash is. That's what makes it cheaper.

The DRAM chips don't actually have to be cheaper. They just need to enable the system as a whole to be more cost effective. If putting a bit more logic in the DRAM makes it significantly cheaper and quicker to design and validate a processor's memory controller, and enables better performance and power efficiency from the memory, then it's very likely a net win even if the marginal cost of DRAM chips went up slightly.

Lramseyer 4y ago
While you're correct that overall system cost is what matters, most functionality is offloaded to the controller because a single controller often controls multiple DRAM chips (Like the chips all share a CA bus[1]) So it's cheaper to put the functionality in the controller. With that being said, it gets a bit nuanced, because as we make faster and faster DRAMs, we need more complicated input/output electronics (Phy and ECC.) GDDR actually has self refresh as part of the spec and even allows DRAM vendors to put a PLL inside so you can run a half rate clock, which technically makes it "Quadruple Data Rate" instead of "Double Data Rate." But usually with GDDR, you're running one controller per DRAM. Clamshell mode is not super common in my experience. [1] I'm not super well versed on DDR4 and all of its configurations. So someone who is can elaborate if they would like.

londons_explore 4y ago

Putting a controller in the dram allows that controller to detect bad memory cells and repair data (ecc-like) or re-map data to other addresses. Both of those things would be possible while implementing the regular 'dumb' dram interface, but any error detection or remapping would have to operate within the latency budget of the module, since the latency is fixed. Typically that means not much remapping can be done, and ram yields have to be really good. With this change, ram becomes robust to far more silicon defects like nand flash is. That's what makes it cheaper.