Please do not resort to personal attacks, we are just having a technical discussion. In intel parlance 'serializing instruction' is a Word of Power; Please see

Please do not resort to personal attacks, we are just having a technical discussion. In intel parlance 'serializing instruction' is a Word of Power; Please see Vol 3A, under serializing instructions. CPUID is listed there. In the same section, LFENCE, MFENCE, SFENCE are listed as 'memory ordering instructions' and the documentation explicitly says that: The following instructions are memory-ordering instructions, not serializing instructions. These drain the data memory subsystem. They do not serialize the instruction execution stream Handling self modifying code requires serializing the instruction stream, so the memory fences are neither necessary nor sufficient[1]. Going back to the original argument, the memory fence instructions (and the various LOCK prefixed operations) do indeed serialize memory operations to guarantee ordering, which I don't dispute. But that's nothing to do with synchronizing caches like you claimed. [1] IIRC MFENCE it is actually also a serializing instruction in practice, but Intel has not yet committed to document this behavior as architectural.