4 ms·

A few years ago I would have agreed with this hierarchy but having recently replaced my relatively powerful i7 laptop with an ARM based one and experienced a si

A few years ago I would have agreed with this hierarchy but having recently replaced my relatively powerful i7 laptop with an ARM based one and experienced a significant improvement in my use cases, I’d say ARM most definitely poses a threat to x86 for the majority of consumer use cases.

philosopher1234 4y ago
I think that was actually their point. There will be a RISCV rampage
- fwsgonzo 4y ago
  The vector extension in RISC-V is extremely powerful, and I think it will be very interesting to see what can be done with it in a desktop or server CPU down the road.
  - brucehoult 4y ago
    It is. SVE is very similar too. It's going to be interesting between then, because they are both coming out of the blocks at about the same time. The only consumers who have SVE now are owners of this year's phones with the Snapdragon 8 Gen 1 (Galaxy S22, Xiaomi 12, ...), where it is buried so deep few will be aware of or playing with it. No one at all has mass-production RISC-V vector extension 1.0 just yet. Two popular Chinese SBC makers have said in chat rooms that boards they will announce (maybe even ship) in December do (and with quad 2.5 GHz OoO cores!) I'm slightly dubious but we will see. In any case, some will be coming in 2023 -- and in laptops, not only SBCs. Quite a lot of people have bought cheap RISC-V SBCs using the Allwinner D1 SoC, which implements draft version 0.7.1 of the RISC-V vector extension. Most instructions are unchanged (in both mnemonics and binary encoding) between 0.7.1 and 1.0 but enough very important instructions have changed -- vsetvli and loads and stores, for example -- that code needs to be tweaked to move between them. But 0.7.1 is good practice, and boards start from $17 (1 GHz single core with 512 MB RAM, very similar to a Raspberry Pi Zero) which is a lot cheaper than a sacrificial Galaxy S22.
kyriakos 4y ago
The point here is that risc V will do the same to arm that arm is doing to x86, therefore arm shouldn't underestimate the competition.
makapuf 4y ago
Well if the ARM laptop is Apple silicon, ARM poses a threat for the majority of Apple consumer use cases.
RobotToaster 4y ago
I still don't understand how RISC machines can outperform CISC ones on the desktop. Is it just the intel/AMD duopoly causing stagnation? or something fundamental?
- qwytw 4y ago
  I think Apple just designed a better CPU than AMD and Intel could due to a variety of reasons. The fact that it's ARM seems to be mostly tangential if Apple if had access to another architecture and invested a similar amount of money and resources into it for over 10 years the result would probably be similar. It’s not like Qualcomm or any other ARM manufacturer has anything remotely close to M-series SoC.
- mavhc 4y ago
  a) It's not on the desktop, it's on the laptop b) CISC machines are just RISC machines with an extra layer of decoding c) Bringing your CPU design in house means it can interface better with your hardware and software d) cost
- dkjaudyeqooe 4y ago
  The whole point of RISC is that it's faster than CISC. It doesn't matter where.
- todd8 4y ago
  Back in the mid 80's, I was an operating system architect at IBM during the first couple of versions of AIX (IBM's Unix system). This ran on a new RISC architecture that is now called POWER. The idea for RISC came from the realization that complex instructions in a CISC processor still had to run a set of lower level functions provided by the hardware. Consider, for example, the CISC architecture of the DEC PDP-11 computer (the system that Unix was originally developed on). It's indirect addressing modes where used to store or load from an address found in a register; this is a frequently used addressing mode on both RISC and CISC machines. However, the PDP-11, being a CISC machine, had eight variations of indirect addressing that automatically incremented/decremented the memory address in the register by one or two, before or after the location was used, etc. As an assembly language programmer I liked this because it seemed like I could get more work done in a single instruction when I was iterating over an array of data. However, this is an illusion. The hardware still had to do the work so that single instruction using autoincrement indirect addressing took more time to run. RISC machines generally have a few very simple load and store instructions to access memory and most other instruction work on registers alone. The underlying hardware is more straight forward. The instructions have more predictable running time. It is easier to perform out of order execution and speculative execution since the instructions can be arranged to use non-overlapping set of registers. For these reasons, the researchers developing RISC believed that they could achieve the same speed as CISC by running more instructions each running a bit faster than CISC instructions. At this point, one might think that it is kind of a six of one, half-dozen kind of comparison where there is no clear advantage. But RISC has another advantage over CISC. Because the hardware is so straight forward it is easier for compilers to do very sophisticated optimizations. CISC computers often have special registers used by certain instructions differently than other registers. RISC computers usually have a larger number of basically identical registers. This makes register allocation much easier for compilers. On RISC computers, the instructions are often all of the same size again making it easier for compilers to arrange the instructions to fit better in the highest performing cache memory. The idea is that RISC is friendlier to compilers, and the combination of the fast simple instructions and advanced compilers will outperform the CISC machines. This all sounds good and I consider IBM's POWER and the ARM architecture a success, but Intel is full of very smart people and they have proven that it's not entirely clear that RISC is better than CISC. Some complex instructions are just very useful, like Intel's vectorization instructions and the 2013 instructions that accelerate the calculation of SHA and SHA-256. Lot's of factors are important in general purpose processor designs: virtual memory support (IBM's POWER has an inverted page table design for example), multiple compute units, virtualization, multicore, caches, good support for JIT compiler designs not just the AOT compilers envisioned when RISC was first being developed. Intel's success and the need for backward compatability has shackled its current designs, and they have done very well despite this. Although I like the idea of a simpler faster architecture (RISC), Intel might be developing their own next generation processor architecture right now because this would fend off RISC-v and AMD too. They might come out with a new design that was RISC or CISC or a hybrid; it might even be wildly different like a very long instruction architecture.

philosopher1234 4y ago

I think that was actually their point. There will be a RISCV rampage

fwsgonzo 4y ago
The vector extension in RISC-V is extremely powerful, and I think it will be very interesting to see what can be done with it in a desktop or server CPU down the road.
- brucehoult 4y ago
  It is. SVE is very similar too. It's going to be interesting between then, because they are both coming out of the blocks at about the same time. The only consumers who have SVE now are owners of this year's phones with the Snapdragon 8 Gen 1 (Galaxy S22, Xiaomi 12, ...), where it is buried so deep few will be aware of or playing with it. No one at all has mass-production RISC-V vector extension 1.0 just yet. Two popular Chinese SBC makers have said in chat rooms that boards they will announce (maybe even ship) in December do (and with quad 2.5 GHz OoO cores!) I'm slightly dubious but we will see. In any case, some will be coming in 2023 -- and in laptops, not only SBCs. Quite a lot of people have bought cheap RISC-V SBCs using the Allwinner D1 SoC, which implements draft version 0.7.1 of the RISC-V vector extension. Most instructions are unchanged (in both mnemonics and binary encoding) between 0.7.1 and 1.0 but enough very important instructions have changed -- vsetvli and loads and stores, for example -- that code needs to be tweaked to move between them. But 0.7.1 is good practice, and boards start from $17 (1 GHz single core with 512 MB RAM, very similar to a Raspberry Pi Zero) which is a lot cheaper than a sacrificial Galaxy S22.

kyriakos 4y ago

The point here is that risc V will do the same to arm that arm is doing to x86, therefore arm shouldn't underestimate the competition.

makapuf 4y ago

Well if the ARM laptop is Apple silicon, ARM poses a threat for the majority of Apple consumer use cases.

RobotToaster 4y ago

I still don't understand how RISC machines can outperform CISC ones on the desktop. Is it just the intel/AMD duopoly causing stagnation? or something fundamental?

qwytw 4y ago
I think Apple just designed a better CPU than AMD and Intel could due to a variety of reasons. The fact that it's ARM seems to be mostly tangential if Apple if had access to another architecture and invested a similar amount of money and resources into it for over 10 years the result would probably be similar. It’s not like Qualcomm or any other ARM manufacturer has anything remotely close to M-series SoC.
mavhc 4y ago
a) It's not on the desktop, it's on the laptop b) CISC machines are just RISC machines with an extra layer of decoding c) Bringing your CPU design in house means it can interface better with your hardware and software d) cost
dkjaudyeqooe 4y ago
The whole point of RISC is that it's faster than CISC. It doesn't matter where.
todd8 4y ago
Back in the mid 80's, I was an operating system architect at IBM during the first couple of versions of AIX (IBM's Unix system). This ran on a new RISC architecture that is now called POWER. The idea for RISC came from the realization that complex instructions in a CISC processor still had to run a set of lower level functions provided by the hardware. Consider, for example, the CISC architecture of the DEC PDP-11 computer (the system that Unix was originally developed on). It's indirect addressing modes where used to store or load from an address found in a register; this is a frequently used addressing mode on both RISC and CISC machines. However, the PDP-11, being a CISC machine, had eight variations of indirect addressing that automatically incremented/decremented the memory address in the register by one or two, before or after the location was used, etc. As an assembly language programmer I liked this because it seemed like I could get more work done in a single instruction when I was iterating over an array of data. However, this is an illusion. The hardware still had to do the work so that single instruction using autoincrement indirect addressing took more time to run. RISC machines generally have a few very simple load and store instructions to access memory and most other instruction work on registers alone. The underlying hardware is more straight forward. The instructions have more predictable running time. It is easier to perform out of order execution and speculative execution since the instructions can be arranged to use non-overlapping set of registers. For these reasons, the researchers developing RISC believed that they could achieve the same speed as CISC by running more instructions each running a bit faster than CISC instructions. At this point, one might think that it is kind of a six of one, half-dozen kind of comparison where there is no clear advantage. But RISC has another advantage over CISC. Because the hardware is so straight forward it is easier for compilers to do very sophisticated optimizations. CISC computers often have special registers used by certain instructions differently than other registers. RISC computers usually have a larger number of basically identical registers. This makes register allocation much easier for compilers. On RISC computers, the instructions are often all of the same size again making it easier for compilers to arrange the instructions to fit better in the highest performing cache memory. The idea is that RISC is friendlier to compilers, and the combination of the fast simple instructions and advanced compilers will outperform the CISC machines. This all sounds good and I consider IBM's POWER and the ARM architecture a success, but Intel is full of very smart people and they have proven that it's not entirely clear that RISC is better than CISC. Some complex instructions are just very useful, like Intel's vectorization instructions and the 2013 instructions that accelerate the calculation of SHA and SHA-256. Lot's of factors are important in general purpose processor designs: virtual memory support (IBM's POWER has an inverted page table design for example), multiple compute units, virtualization, multicore, caches, good support for JIT compiler designs not just the AOT compilers envisioned when RISC was first being developed. Intel's success and the need for backward compatability has shackled its current designs, and they have done very well despite this. Although I like the idea of a simpler faster architecture (RISC), Intel might be developing their own next generation processor architecture right now because this would fend off RISC-v and AMD too. They might come out with a new design that was RISC or CISC or a hybrid; it might even be wildly different like a very long instruction architecture.