For PTX: For sm_70 onwards (which is the arch that comes with tensor cores) NVIDIA made the task significantly harder. Those newer architectures use a separat

For PTX: For sm_70 onwards (which is the arch that comes with tensor cores) NVIDIA made the task significantly harder. Those newer architectures use a separate instruction pointer per thread/lane, for notably supporting C++ atomics across threads in the same warp without deadlocks. This doesn't match the semantics present on AMD GPUs. For HIP/ROCm: I think that they need an abstraction layer that can make a single slice of binary code that is usable across multiple gens. Compounded by the fact that different dies have different binary slices on the AMD side, so that 6800 XT and 6700 XT run different code slices. ROCm only supports Navi21 cards for RDNA2, not the other ones... For oneAPI, OpenCL SPIR-V fulfills that role.