I wonder how much the misapprehension that FPGAs somehow emulate is due to the fact that the way we configure them looks so much like code. VHDL is ghastly, but

I wonder how much the misapprehension that FPGAs somehow emulate is due to the fact that the way we configure them looks so much like code. VHDL is ghastly, but I prefer it over verilog bc verilog seems to actually try to look like C. I think especially for beginners it's too easy to lose sight of the fact that while you may "read through" your VHDL/verilog, that when it hits the FPGA fabric it's all going to happen in parallel. Maybe if the source matter were made to resemble data more than code, we could simultaneously ditch the verbosity of VHDL and the imperative algorithm appearances of verilog. I'm thinking maybe JSON at the moment. =P