9 ms·

> I think it's great the author made an account today on HN, and is replying to questions from his post. This is one if the best parts of the community here. :

> I think it's great the author made an account today on HN, and is replying to questions from his post. This is one if the best parts of the community here. :) > I would love to see some test done on newer CPUs So, the site is a free time thing run by several people, all of which are either students or have other full time jobs (not full time reviewers with samples of the latest hardware). No one happened to have an ICL/TGL/ADL CPU available. I do have an ADL result from earlier today showing full boost after 0.5 ms, but that person also overclocked and may have used a static voltage. Maybe we can get an addenum out with more results but I wouldn't bet on it. And yeah probably. In an extreme scenario you could just lock the CPU to its highest clock. Then you'll never see a transition period at all. > logged the PSU I don't have a power meter or PSU capable of logging

jeffbee 4y ago
Big fan of your site. Travis Downs has done some work on characterizing hardware transition latency. I believe his tools are on GitHub. https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html
- clamchowder 4y ago
  Yeah, he has some pretty interesting stuff. But AVX512 transition latency is pretty different from clocking up from idle. The CPU is already running at full tilt, and is making a relatively small frequency/voltage change. You can see from his writeup that it's well under a millisecond. I believe newer Intel CPUs have done away with AVX-512 downclocking completely. I probably won't be able to look into that specific issue since I don't have any AVX-512 capable CPUs.
  - jeffbee 4y ago
    Yeah I think his insights still apply, though. The difference between a FIVR part and other parts might be significant, and since the CPU has to wait for the VR to settle it might not be appropriate to ascribe state transition latency entirely to the CPU generation. It’s really the whole platform.

jeffbee 4y ago

Big fan of your site. Travis Downs has done some work on characterizing hardware transition latency. I believe his tools are on GitHub. https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

clamchowder 4y ago
Yeah, he has some pretty interesting stuff. But AVX512 transition latency is pretty different from clocking up from idle. The CPU is already running at full tilt, and is making a relatively small frequency/voltage change. You can see from his writeup that it's well under a millisecond. I believe newer Intel CPUs have done away with AVX-512 downclocking completely. I probably won't be able to look into that specific issue since I don't have any AVX-512 capable CPUs.
- jeffbee 4y ago
  Yeah I think his insights still apply, though. The difference between a FIVR part and other parts might be significant, and since the CPU has to wait for the VR to settle it might not be appropriate to ascribe state transition latency entirely to the CPU generation. It’s really the whole platform.