4 ms·
Are these tools able to handle the Xilinx blocks like BUFGMUX_CTRL? Or I should still have fun by myself? That makes the difference. Writing plain VHDL and cons
by lnsru 4y ago
Are these tools able to handle the Xilinx blocks like BUFGMUX_CTRL? Or I should still have fun by myself? That makes the difference. Writing plain VHDL and constraints is the smallest pain point for me.
- dayjaby 4y agoYes, you can use existing blocks and IPs. E.g. if you use the f4pga+migen+LiteX stack, this looks like this in the end: https://github.com/enjoy-digital/litex/blob/d36f98bf45c20e2f1895abd4aadf528bf129db11/litex/soc/cores/ram/xilinx_fifo_sync_macro.py#L38 https://github.com/enjoy-digital/litex/blob/d36f98bf45c20e2f...