3 ms·
> Sadly, Qualcomm was very bad at implementing caches, but that’s a story for another day. Anyone know what that story is?
by johntb86 4y ago
> Sadly, Qualcomm was very bad at implementing caches, but that’s a story for another day.
Anyone know what that story is?
- clamchowder 4y agoBig cores each have a 512 KB L2 cache with a latency of around 24 cycles, while the little ones each have a 256 KB L2 with ~23 cycle latency. It's really terrible considering the low 2.34/1.6 GHz clock speeds. Then there's no multi-megabyte last level cache, so it's going out to memory a lot. They do have 3 cycle L1D latency, but again that's at low clocks, and it's a 24 KB L1D so it's 25% smaller than most L1Ds we see today. Not great considering you're eating 20+ cycle L2 latency once you miss the L1D, unlike most CPUs today that have 12 cycle latency for 256 or 512 KB L2s.