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One of the main value adds of an open ISA + open reference implementations Chisel/Chipyard + access to RTL (I think?) is that LOTS of people are hungry for rea
by dwrodri 4y ago
One of the main value adds of an open ISA + open reference implementations Chisel/Chipyard + access to RTL (I think?) is that LOTS of people are hungry for really good multi-core out-of-order CPU pipelines with super-stringent levels of provable correctness. I think the tooling ecosystem is on the right track in terms of providing a FOSS toolchain that supports this. It's not there yet, but you're average ECE master's student could probably teach themselves chipyard and start their own Rocket fork which is much easier to test/verify at the basic-block level than a lot of other tooling I've used.
- brucehoult 4y agoNote that X280 is not OoO. It's the same proven dual-issue in-order U74 core (similar to ARM A55) what has been out for a few years, and is just now hitting Raspberry Pi levels of price in the VisionFive 2 and Pine64 Star64. The X280 just has an added RISC-V Vector unit.
- whazor 4y agoAlso because the CPU layout is generated by software, maybe it is easier to add custom constraints specific for space.