To add onto this you can easily increase the clock for specific clock domains using a PLL (Phase locked loop) as a clock multiplier. This comes with all kinds

To add onto this you can easily increase the clock for specific clock domains using a PLL (Phase locked loop) as a clock multiplier. This comes with all kinds of caveats and complications(PLL clock multiplication is "fuzzy" and subject to phase drift and variations in actual frequency while normal clock division is essentially as close to exact as you can really get). Because of this, like mentioned it's preferable to use clock division instead of clock multiplication where possible.