4 ms·
Signal integrity first, then maybe cost or power usage. Commercial state of the art is around 100Gbit/s per pair using a gearbox chip, as seen in 100G single la
by gaudat 4y ago
Signal integrity first, then maybe cost or power usage. Commercial state of the art is around 100Gbit/s per pair using a gearbox chip, as seen in 100G single lambda transceivers. For ASIC/FPGA i think 58GHz PAM4 is available giving 116Gbps per pair. Actual data rate will be a few percent lower due to line coding and forward error correction.
Normal circuit boards start interacting with the signal from about a few gigahertz. At really fast rates you need some black magic like Teflon or ceramic substrates for the signal to even get through.
- sylware 4y agoWell, the EM environment would be a CPU die on a motherboard full of gigahertz chips, it means this EM environment has been so much "improved" they can double the speed?? I am really curious at how they choose to limit the speed of USB lanes, that said I really don't like that as this smells "don't go too fast or we won't be able to sell USB controllers with really faster lanes". I would understand if one of the major limiting elements is the controller silicium process (2nm/5nm/etc).