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> I have no idea what ARM's thinking at this point. Focussing on desktop and servers.. It worked. In a similar fashion RISC-V has things which makes little se
by renox 4y ago
> I have no idea what ARM's thinking at this point.
Focussing on desktop and servers.. It worked.
In a similar fashion RISC-V has things which makes little sense for "high performance" (16-bit aligned 32bit instructions with the C extension, too simple addressing mode) which shows that their main goal is embedded..
- snvzz 4y ago>has things which makes little sense for "high performance" Such as? >(16-bit aligned 32bit instructions with the C extension) For virtually no cost (see brucehoult reply to my parent post), it brings greatly increased code density, which means more code fits in L1, or same thing, that you can make it smaller and clock it higher. This actually benefits high performance microarchitectures greatly. See M1's L1 size for an example of why ARMv9 AArch64 is mind-blowingly bad. ARM's literally lost its marbles. >(too simple addressing mode) More complex addressing modes were evaluated and discarded, as they only brought harm, no benefit. This is a pattern in RISC-V, where decisions were made after careful weighting, rather than some individual's favored way of doing things.