Materially better, how? Aarch64 instructions are on average bigger than RISC-V ones and sometimes do slightly more work, but the complicated ones are split int

Materially better, how? Aarch64 instructions are on average bigger than RISC-V ones and sometimes do slightly more work, but the complicated ones are split into µops and the number of clock cycles ends up similar. RISC-V code is demonstrably a lot more compact than ARM -- download any Linux distro that supports both (Debian/Ubuntu, Fedora...) and compare binary sizes. The RISC-V ones are consistently 20%+ smaller, despite currently still using the original RV64GC ISA. Binaries using the new stuff ratified in November last year will be smaller again. In similar µarches, RISC-V cores are faster than ARM cores. The SiFive U74 is faster than the ARM A55 (not to mention A53). The P550 is faster than the A76. M1-class RISC-V is coming -- often worked on (e.g. at Rivos) by many of the same engineers and managers who made M1. Nuvia was ARM's great hope for a competitive core that wasn't Apple-internal. I don't see how ARM can make Nuvia delete their plans. They can stop them selling the results, sure. What prevents Qualcomm converting the existing µarch work to RISC-V? Nothing that I can see. The ISA are very similar. It's mostly just a different instruction decoder and CSRs and delete a few things such as the condition codes.