4 ms·
>and cache, for instance. A necessity. ARM code density is awful, thus a huge L1 is needed to compensate. This is costly, and ARM's Achilles heel.
by snvzz 4y ago
>and cache, for instance.
A necessity. ARM code density is awful, thus a huge L1 is needed to compensate.
This is costly, and ARM's Achilles heel.
- GeekyBear 4y ago>No, x86-64 is just as inefficient as AArch64 these days, because of all the REX prefixes. Almost every instruction needs one and it bloats the size tremendously, to the extent that most x86-64 instructions are just about 4 bytes. https://news.ycombinator.com/item?id=19329128 https://news.ycombinator.com/item?id=19329128
- snvzz 4y agoAbsolutely. x86-64's code density is shit. But so is AArch64. The point being, it is a bottleneck and it's possible to do far better. RISC-V has (by far) the best code density among 64bit ISAs.