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Forth Inventor Chuck Moore's $20 144 core CPU now in full production
- csmeder 15y agoYou can buy a 10 pack of evaluation chips from Green Array's web site or single from schmartboard's website http://www.schmartboard.com/index.asp?page=products_csp&id=532 http://www.schmartboard.com/index.asp?page=products_csp&...
- kiba 15y agoLet me get this straight: It's basically a microcontroller timed 144? Can anyone explain to a nonhardware geek?
- chalst 15y agoThis example gives something of an idea: http://www.greenarraychips.com/home/documents/pub/AP002-OSC.html http://www.greenarraychips.com/home/documents/pub/AP002-OSC.... The picture I get is that the boundary between computing components and control/sensor electronics is dissolved.
- zackmorris 15y agoI've done many write-ups on this if you look under my profile. Basically the idea is that most of the big problems in software engineering can't be solved easily in a serial fashion with current methodologies, and many of the existing parallel solutions are either too expensive or two complicated to advance the state of the art. I wish I had this chip 15 years ago...
- femto 15y agoIt's the future, representing a convergence between Field Programmable Gate Arrays (FPGAs) and the microprocessor. Gate arrays are vast arrays of logic gates, which can be wired together in almost arbitrary patterns by a sea of "fuses", typically controlled by state stored in on-board SRAM. They are real time and blindingly fast due to their massive parallelism, achieving supercomputer type speeds when applied to the right type of problem and programmed well. They are more difficult to program than a microprocessor. One way of looking at an FPGA is as an array of tens of millions of very simple computing engines. Over the years, the number of transistors on an FPGA has been rocketing up. Generally these transistors have been put to use by providing more and more simple logic blocks. We are now to the point where we have almost more gates than we know what to do with, and the chip is being dominated by interconnects. This has seen a move towards including a limited number of elaborate hard wired blocks, such as CPUs and multipliers, in addition to the array of logic. The logical evolution is to stop providing more blocks, but make each block more complex as transistor counts go up. Eventually we will see arrays of tens of millions of microprocessors, rather than tens of millions of logic blocks. There will be no distinction between a multicore CPU and FPGA. It's worth noting that the first Xilinx FPGAs, thirty years ago, provided arrays of around 144 logic blocks, similar to the processor count in this chip. Extrapolate 30 years and we will have an array of 10 million microprocessors.
- femto 15y agoCorrection: I've been lax in my terminology with logic gates and cells. Current big FPGAs contain around 2 million "logic cells", which typically represent between 1 and 10 logic gates each, depending on device programming.
- sliverstorm 15y agoUnfortunately for the FPGA guys, it seems like in general the closer they get to CPUs the less compelling their product becomes.
- femto 15y agoI hesitate to divide the world into "FPGA guys" and "non-FPGA guys". It's a continuum of computing power; CPU<->DSP<->FPGA, and one moves up and down it as the task varies and technology changes. If anything defines an "FPGA guy" is choice of language. Historically FPGAs have been programmed with an HDL, such as VHDL or Verilog, because these languages are concurrent meaning they handle parallel systems. My prediction is that as mainstream multicore CPUs develop we will see the rise of concurrent versions of mainstream languages, which will supplant HDLs. Just as DSP's are now programmed in (almost) vanilla C/C++/..., we will see FPGAs being programmed using the same languages as micros and DSPs. It will then be possible to write code and (almost) seamlessly run it on any platform, depending on how fast it needs to run.
- sliverstorm 15y agoBy "FPGA guys" I meant the guys who make FPGAs, not the guys who use them. There is still a pretty strong dividing line between FPGAs and DSP chips.
- femto 15y agoSorry for the misinterpretation. If I was an FPGA manufacturer, I'd be trying to buy a company like Green Array and beat the CPU manufacturers to the middle ground. Agree about the current divide, though I think it will weaken and eventually disappear.
- neopanz 15y agoLove the guy and his passion for its chips, but this 144-computer chip looks like a solution in search of a problem: what is trying to solve? How's the inter-core communication handled? On the other hand, creating weird chips like these, just because you can, is awesome and stimulating a hacker's mind.
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- 101001010111 15y agoNot sure if it's a legitimate "problem" or not, but how about the availability of single chips, or 10-packs? Assuming someone wanted to produce a prototype board, but didn't want to purchase 1000's of CPU chips, are there many CPU chip makers who offer low quantities like this?
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- swdunlop 15y agoIt appears that CM's intent with the F18A core is to create an extremely low power processor that scales the number of cores to the complexity of the problem being addressed -- look at the reference sheets about what the requirements are to maintain core states. The design makes more sense when you stop trying to think of it as an ARM or AVR competitor, and more like a replacement for FPGA's.
- 6ren 15y agoSome of the industries greatest advances have began as a solution in search of a problem, such as the microprocessor (which its inventor, Intel, didn't think much of compared with memory chips where the real money was). Most fail of course. If someone can make many-core, in this form, do something useful that can't be done elsewhere (unlike DSP and GPUs, which are already many-core), it will fundamentally upend computing.
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- neopanz 15y agoI think the only thing Chuck is missing is a few 20-somethings hackers, bent on solving an 'impossible' problem with his chips.
- csmeder 15y agoThat's why I'm posting it here. Some possible ideas ==================== - Sound processing (think 144 cores preforming Fourier Transforms) - Pico Satellites (This chip has a surprisingly extreme low power requirement). - Wireless communication (small power requirement means small batteries) - Computer Vision processing. Imagine toys or tools that can process visual information faster than an Xbox. - Basically anything that can be done in parallel, that is suited for small size and low power, but doesn't require much on chip memory.
- ippisl 15y agoHad a rough look on it's instruction set and didn't see anything resembling DSP instructions. So i'm not sure it would be great for all those uses. On the other hand, picochip sells a 200-300 core DSP , that is being used for the wireless industry.
- csmeder 15y agoFrom this PDF http://www.greenarraychips.com/home/documents/greg/PB001-100503-GA144-1-10.pdf http://www.greenarraychips.com/home/documents/greg/PB001-100... GreenArrays seems to think it would support DSP "SUITABILITY: The GA144 is designed to support the largest and most demanding computing challenges that can be addressed with a modest sized die in a relatively inexpensive and easy to use package while still using well less than 650 mW in most practical applications. The geometry allows for generous numbers of parallel paths and/or pipeline stages, or for complex flowgraphs in control, simulation, or DSP applications. Clusters of nodes devoted to functions such as cryptographic algorithms are easily placed in the large array, and the cluster needed to control external memory and run a high level language from it is well out of the way but has good surface area for interaction with other functions. Use it also as a universal protoytping platform for applications destined to run on our smaller chips. "
- neopanz 15y agoMay be if you use 100+ of these (~14400 'computers') you can build a machine with emerging behavior, brain-like?
- ypcx 15y agoI knew it. The name "Moore" sounded suspicious to me immediately. Now I know his real name is Chuck Testa!!! On a more serious note, what we need much more of is not the processing speed. What we need much more of is what I call "memory processability", which roughly means "how many times per second can you process the whole memory" - or something like that. Basically how much CPU is there per RAM. Indexing is a great hack, but a hack it still is. Memory and processing cells must be merged into a single, massively parallel chip.
- thisrod 15y agoThat was done in the 80's: http://en.wikipedia.org/wiki/Connection_Machine http://en.wikipedia.org/wiki/Connection_Machine . Richard Feynman had to help the designers with the hard bits. Users recall them fondly. In the end, clusters became too cheap for custom hardware like this to compete.
- itsameta4 15y ago>What we need much more of is what I call "memory processability", which roughly means "how many times per second can you process the whole memory" I might be misinterpreting, but I think the phrase you're looking for is "memory bandwidth".
- sliverstorm 15y agoIf 15,000 computers was all you needed for AI, we'd have it by now. Major datacenters have way more machines than that, which are far more powerful than a milliwatt microcontroller to boot.
- scottyallen 15y agoNot being much of a hardware geek, I'm having a hard time evaluating how fast each core is. From the site: "With instruction times as low as 1400 picoseconds and consuming as little as 7 picojoules of energy, each of the 144 computers can do its work with unprecedented speed for a microcontroller and yet at unprecedentedly low energy cost, transitioning between running and suspended states in gate delay times. When suspended, each of the computers uses less than 100 nanowatts." How does this instruction time compare to other modern processors? It sounds to me like some of the benefit to be had here may be from the low amount of power necessary per core. Power and associated cooling is a MAJOR source of cost for datacenters, and so if this really is a significantly lower power consumption (again, I don't know how much power the alternatives use), then it could have a big impact on the cost of commodity computation power.
- _delirium 15y agoIf 1400 picoseconds is the time it takes for a clock cycle (and therefore the minimum instruction time for 1-cycle instructions), that'd be about 700 MHz, which actually seems pretty high compared to what I would've guessed.
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- neuraxon77 15y agoAs far as I know, the cores aren't clocked. Instead Chuck designed his own transistors using his own OKAD II VLSI tools to be efficient on the CMOS process node with switching speeds being dictated by the transistor type and interconnect electrical properties, then designed the cores so that they're only switching those transistors when they do actual work.
- Symmetry 15y agoOoh, awesome. Clockless computing seems like a really nifty idea, but its difficult. I imagine it might go mainstream when Moore's law finally runs out.
- ChuckMcM 15y agoWell if you ever wanted to be 'out there' Chuck's processor would be a great place to start. Chuck Moore invented Forth and has been building machines that can run Forth efficiently for years. Think of it as a Turing machine that can do useful work. He has pushed the edge of computation per watt for years. That being said, I've heard him talk about this chips for years and it is great to see it finally see the light of day. If you were familiar with the Transputer technology, this is a better take on that, if you are familar with FPGAs you can think of it as an FPGA with processors instead of CLBs. Things that it can do are similar to what Intel is doing with Larrabee or some of the CUDA stuff that nVidia has done. It doesn't have a GDDR3 interface to a GB of memory so you can't custom build your own GPU, but you could do your own PhysX type engine with it. It also makes a helluva differential cryptanalysis tool, or a signals analysis tool in general.
- 6ren 15y agoCLB = configurable logic blocks
- joelthelion 15y agoIt might make a good bitcoin mining platform?
- pnathan 15y agoI have done my Master's work with the XCore (xmos.com), which is a direct descendant of the Transputer. It's programmed in an C-with-CSP-constructs called XC. I found it very easy to write XC correctly. I think that the CSP/transputer idea is really the best way for most parallel programming to happen. MPI and pthreads allow more flexibility, but in most (say, 80%) of cases, that's not needed for your application.
- protomyth 15y agoThe Propeller chip http://www.parallax.com/propeller/ http://www.parallax.com/propeller/ is another embedded market chip in the same vein although nowhere near as many cores. Having something like this make for some interesting embedded designs. Also, check the site for the arrayForth stuff. On another note, it would be interesting if something like these existed in the 64-bit size. Larrabee is interesting, but if it was a simpler stack machine at around this price point then perhaps some work could be done on different ways to do parallelism.
- ippisl 15y agoTilera does a 64-bit CPU with 64/100cores.If they would offer access to it using a pay-per-hour model, that would be interesting.
- dkersten 15y agoI spoke to one of the Tilera guys a few years back about evaluating their boards for use in a telco project I was working on at the time, but gave up because I wasn't prepared to drop $15K on a development board just to evaluate it. The technology itself was extremely interesting, though, and would probably have been a good fit for what I was doing. Also, the cost of the dev board included technical support and from speaking to the guy, I got the impression that they actually help you port your code to their platform.
- ww520 15y agoWhat are the software stacks that are available on the chip? Forth must be there. Anything else?
- rbanffy 15y agoWondering if it ciuld emulate an Apple Ii in real time and, within it, run GraFORTH.
- jxcole 15y agoI think this sounds ridiculously cool and at $20 I could probably afford to play around with it. But I have no knowledge of hardware, just programming. To me chips just look like thin green rectangular prisms. How would I get it to actually, you know, do stuff?
- ars 15y agoYou would probably want to buy the Evaluation Board which lets you control the machine using USB ports and an ASCII console. The thing is, it's just a computer. The real value of this is hooking it to hardware to actually do something. So I suggest starting here instead: http://www.greenarraychips.com/home/documents/budget.html http://www.greenarraychips.com/home/documents/budget.html and learning how to work with hardware as well.
- makmanalp 15y agoyou can do this for about $30: http://www.greenarraychips.com/home/documents/budget.html http://www.greenarraychips.com/home/documents/budget.html "suggestion for a complete system"
- defen 15y agoCall up Woz, I hear he was good at that stuff.
- sausagefeet 15y agoIs this something I would use in the place of something like an Arduino (for example, putting a brain on an RC car)?
- Symmetry 15y agoIn past Forth threads I've complained the the Forth model for a computer seems just too at odds with how modern CPUs actually work for me to want to learn it. Well, I look at this thing and its like the soft draft of the future slipping underneath the door, whispering that maybe I should learn Forth after all.
- dkersten 15y agoIts worth noting that a number of popular VM's, eg, the JVM, have Forth-like stack-based instruction sets.
- derleth 15y agoOTOH, LLVM is, if anything, a register machine, so as to better map to the register machines we're implementing in hardware right now.
- dkersten 15y agoYes, LLVM is a register machine and CPUs are register machines. My point really was that one shouldn't avoid stack-based languages or virtual machines because CPUs don't work that way, since some of the most used and most popular virtual machines are stack machines and get by just fine. (AFAIK both JVM and CLR are stack-based)
- kabdib 15y agoThe big difference between FORTH and other stack machines (e.g., the JVM) is the runtime. FORTH doesn't have one to speak of. No dynamic memory management, no garbage collection. It's about as bare-bones as you can get. PostScript, the JVM, the CLR and so forth are all backed by runtimes with powerful functionality.
- barrkel 15y agoIn practice, the difference between LLVM and a stack machine like CLR or JVM is quite small. LLVM SSA, modulo phi nodes, encodes expressions as DAGs in a completely straightforward sense: every operation names its arguments, and those names serve as unique references to a sub-DAG, since they cannot be reassigned. So given the final operation, you can follow the arguments recursively all the way through, completely transparently. Stack machines like the CLR and JVM encode expressions as trees serialized in a post-order - and to the extent that they use 'dup', they also encode expressions as DAGs. A symbolic interpretation of a CLR or JVM instruction flow, or LLVM SSA instruction flow, can reconstruct the source expression DAG/tree; at which point you can re-encode it using the other approach. And producing output targeting LLVM is even easier than it appears, because you don't need to worry about SSA yourself; just allocate stack locals (with alloca) and use the mem2reg pass to turn it into valid SSA.
- mung7 15y agoThis is all new to me. Does anyone know if these chips could be used for bitcoin mining? However, I believe you would have to write completely new programs if it is possible.
- Don_Wallace 15y agoImagine a Beowulf cluster of those.
- thesz 15y agoI certainly should voice my opinion here. I've done analysis of GA144 before: http://news.ycombinator.com/item?id=1810641 http://news.ycombinator.com/item?id=1810641 Most of the Chuck Moore design (I reviewed several, starting from M17) can be described by quote from Devil Wears Prada: "the same girl- stylish, slender, of course... worships the magazine. But so often, they turn out to be- I don't know- disappointing and, um... stupid". Chuck Moore designs are all slick, slender, stylish, worship Forth, but they turn out to be disappointing and stupid in the end. The only beneficiary often is Chuck Moore itself. You just cannot apply his experience to other places in the world of computing. Let's see what we have here in GA144. The memory inside all cores is way too small for general purpose programs, even if you split your program into 144 parts and spread them across cores. 64 words of RAM, ie, 128 bytes. 128 bytes times 144 - 18Kbytes. Same for the (program) ROM, and you should factor communication code in there. Communication cost affects RAM as well. They offer no compiler from high-level language like C. You had to learn a specific dialect of Forth and some bizarre (albeit small) assembly language. The only benefit for general population from this affair is the relative ease of the desing of asynchronous hardware. http://en.wikipedia.org/wiki/Asynchronous_system http://en.wikipedia.org/wiki/Asynchronous_system
- bitcracker 15y agoYour are focusing on classic applications only. The GA144 is so different from the classic way of computing that it requires new approaches of development. One very interesting feature of GA144 is that all 144 cores can share instructions over I/O lines. That means every core can send instructions to their neighbors who execute them directly without conversion. I/O ist fast enough. I guess it should be possible to have (someday) an external interface to SRAM which circumvents the low memory problem. > They offer no compiler from high-level language like C. That's right, and that's the real weak spot of GA144. Almost every microcontroller board today comes with C or alike. Mr. Moore loves Forth but I doubt that there are many developers out there who like to be forced to learn Forth just for this single platform. I know Forth, it was one of my first languages I ever learned. It is perfectly suitable for embedded systems but you have to learn a lot to master it.
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- honkybozo 15y agoGlad to see this thread. G144A12 does better than you'd expect for 18 bit ALUs doing 32 bit circular shifts and adds, but that costs enough extra instructions that for this particular algorithm at any Bitcoin-useful combination of throughput/energy/cost we can't compete with the genuine 32-bit ALUs of the bigger ATI GPUs. Ya can't be perfect for all problems all the time :) Nevertheless we'll be posting an app note eventually on SHA256 as an illustration of techniques in pipelining. The $20 price is for small quantities. Standard exponential decay curves apply for production quantities; we want to see our chips in people's products and are priced to encourage that. As for 20 somethings, nobody in our company gets a paycheck (yet) so someone has to be willing to work for nothing, but if you have a practical idea for an app note and want to work with us to get it done and published please email greg at greenarraychips dot com and let's discuss it. Thanks for your interest, folks - Greg Bailey, GreenArrays, Inc.