Yeah, cvtsi2sd has 3-9 cycles or latency on Zen3, but throughput ain’t too bad. The table on uops.info says on Zen3, cvtsi2sd has 1 cycle throughput, meaning a

Yeah, cvtsi2sd has 3-9 cycles or latency on Zen3, but throughput ain’t too bad. The table on uops.info says on Zen3, cvtsi2sd has 1 cycle throughput, meaning a core can complete these instructions every cycle. There’s no other dependencies so the pipeline will deal with the latency just fine, by dispatching instructions for multiple loop iterations. It can’t deal with the latency of ARM64 equivalent of addss/addsd due to the dependency chain. I think that’s the bottleneck of the OP’s microbenchmark.