5 ms·

Parallelism can break that speed limit, at least in theory. You could use four different registers to hold x+y, x+2y, x+3y, x+4y and run four instances of the

Parallelism can break that speed limit, at least in theory. You could use four different registers to hold x+y, x+2y, x+3y, x+4y and run four instances of the loop in parallel, if there are no other data dependencies. I'm not sure if hardware microcode can be smart enough to detect that and do it with register renaming and such, but a sufficiently smart compiler could. (Or realistically it would be optimized into SIMD instructions; what I said in the first paragraph is really an ad-hoc implementation of SIMD.)

Const-me 4y ago
> run four instances of the loop in parallel Indeed, here’s an example which uses even higher latency FMA instructions to accumulate: https://stackoverflow.com/a/59495197/126995 https://stackoverflow.com/a/59495197/126995 The example uses 4 independent accumulators to saturate the throughput, instead of stalling on the latency. BTW, on most modern CPUs that code doesn’t saturate the compute throughput, the bottleneck is loads. > a sufficiently smart compiler could They tend to avoid doing that for floats, for accuracy reasons: float addition ain’t associative.
- makapuf 4y ago
  > They tend to avoid doing that for floats, for accuracy reasons: float addition ain’t associative. Indeed, unless you use -ffast-math (also known as -fidontcareaboutthe results). See https://stackoverflow.com/questions/7420665/what-does-gccs-ffast-math-actually-do#22135559 https://stackoverflow.com/questions/7420665/what-does-gccs-f...
  - erik_seaberg 4y ago
    To be fair, lots of devs haven’t studied IEEE 754 error analysis, and don’t know exactly how much precision they can rely on either way. I know I don’t, I just sort of assume the worst.