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> AMD Ryzen 7950X processor enables single-core performance improvement of up to +29% It appears that the new micro architecture is not providing any performan
by tiffanyh 4y ago
> AMD Ryzen 7950X processor enables single-core performance improvement of up to +29%
It appears that the new micro architecture is not providing any performance increase itself since 4.5Ghz is 32% faster than the previous 3.4Ghz clock ... and AMD is measuring a 29% IPC increase.
All of the performance gains must be purely from going to 5nm (vs 7nm).
For reference, the previous chip (5950X) had a base clock of 3.4Ghz [0] and this new 7950X has a base clock of 4.5Ghz.
[0] https://www.amd.com/en/products/cpu/amd-ryzen-9-5950x https://www.amd.com/en/products/cpu/amd-ryzen-9-5950x
EDIT: I'm confused, why the downvotes? Why not just message below if you don't agree with something and we can have a discussion about it.
- KuiN 4y agoYeah there are no major microarchitectural changes that we're aware of for these chips. Bigger L2$, support for AVX-512 (kinda ... double pumping 256bit units), possibly wider front-end but not a huge amount more; it's primarily the new process making the difference.
- adrian_b 4y agoThe support for AVX-512 is not "kinda". AVX-512 at the Ice Lake level is supported. The most widespread Intel CPU with AVX-512 support is Tiger Lake and its support is no better than that of Zen 4, it also provides one 512-bit pipeline for FMA or multiplication and two 512-bit pipelines for simple operations, the same as Zen 4. What happens is that Zen 4 has the same execution units as Zen 3, so any program which can keep all the execution units busy is accelerated on Zen 4 only by the greater clock frequency. However Zen 4 has a new frontend for instruction fetching and decoding and for branch prediction. Many programs will be executed more efficiently than on Zen 3, with a better utilization of the execution units, leading to the claimed IPC improvement of 13% on average. Additionally, rewriting a program to use AVX-512 can also improve the utilization of the execution units, leading to a speed-up greater than the clock frequency ratio. Support for a certain ISA does not imply anything about the speed of the CPU, even if sometimes the CPU vendors change in the same generation both the ISA and the microarchitecture, resulting in greater throughput. In this case AMD has postponed the improvement of the execution units for Zen 5. Even if the support for AVX-512 does not improve the maximum possible throughput, it improves the average throughput over many programs. The same is true for most of the Intel CPUs that support AVX-512, except for the top models of server or workstation CPUs, because they have one of the 512-bit FMA units disabled, which results in the same maximum throughput as on Zen 4 or on the older CPUs, since Haswell.
- zekica 4y agoYou are correct in saying that ISA doesn't matter. The only difference is that it is easier to do 8 instruction parallel pre-fetcher on ARM or another fixed length instruction architecture than on x86_64, and decoding more instructions can be better for re-ordering and register renaming.
- malkia 4y agoDidn't AVX-512 turned out to be a flop? e.g. https://en.wikipedia.org/wiki/AVX-512#Performance https://en.wikipedia.org/wiki/AVX-512#Performance - "On some processors AVX-512 instructions cause a frequency throttling even greater than its predecessors, causing a penalty for mixed workloads. The additional downclocking is triggered by the 512-bit width of vectors and depend on the nature of instructions being executed, and using the 128 or 256-bit part of AVX-512 (AVX-512VL) does not trigger it. As a result, gcc and clang default to prefer using the 256-bit vectors. ()" () - https://stackoverflow.com/questions/56852812/simd-instructions-lowering-cpu-frequency/56859700#56859700 https://stackoverflow.com/questions/56852812/simd-instructio...
- wtallis 4y agoAVX-512 was a bit of a flop initially, because of how Intel implemented it. AMD's solution doesn't provide quite as much peak throughput for highly-optimized code, but is a better way of providing the flexibility benefits of AVX-512 to the masses without the severe downclocking. There may still be plenty of situations where it would make sense to use 256-bit vectors with AVX-512 instructions, but on Zen 4 there won't be a strong reason to avoid 512-bit vectors where they are useful.
- monocasa 4y agoIt was a flop because it was intended for a process node that Intel was delayed on for years. It had massive problems to the point of not really making sense when backported to older nodes.
- wtallis 4y agoI don't think it's accurate to say AVX-512 was backported. The original Skylake consumer CPUs released as the second generation of products on Intel's 14nm already had space reserved in the CPU core floorplan for the AVX-512 register file. That space didn't get used until the Skylake server CPUs shipped, still on 14nm several years later. AVX-512 support didn't arrive in the consumer desktop product line until Rocket Lake, which was backported to 14nm but was not remotely the beginning of the AVX-512 story.
- 4y ago
- ignaloidas 4y agoYou need to improve your micro-architecture to hit those speeds as well. You can't get there without deep pipelines.
- fulafel 4y agoThe uarch affects reachable clock speeds, a lot.
- ben-schaaf 4y agoBase clocks have been basically meaningless for quite a while. My 3700x happily sits at 4GHz on all cores; others see their 5950x at 4.1GHz. It's basically just a number AMD came up with that they want to guarantee under all workloads, not a number that indicates any kind of performance characteristics.
- kolbe 4y agoWhy is it meaningless? It tells you how long a clock cycle takes, and you can look up instructions per cycle for relevant calls. I admit the picture for what makes a fast CPU is highly application dependent and has a lot of variables to consider, but I don't think it's meaningless.
- ben-schaaf 4y agoAs I stated, CPUs don't actually run at the base clock rate. They idle well below and under load they boost above it. How much they boost is of course architecture, load and temperature dependent, but it's generally a fair bit higher than the base clock.
- mibsl 4y agoMeaningless because (adequately cooled) modern desktop CPUs mostly run near their boost clock in single threaded loads and somewhere between base and boost in multithreaded.
- Tuna-Fish 4y ago> It tells you how long a clock cycle takes It does not tell you how long a clock cycle takes. It tells you how long a clock cycle takes when the CPU is massively loaded on all threads, in adverse thermal conditions. If you have better than average cooling, you will never see the base clock under load. If you are running just a single thread, you will always boost to Fmax.
- neogodless 4y agoThis is not accurate. Per their presentation, the geomean of the measured IPC improvement is 13% at a fixed 4.0Ghz comparing Zen 4 to Zen 3. That combined with increased maximum clockspeeds accounts for the up to 29% single-core performance improvement. (Base clock speeds are not relevant or used in their performance comparisons.)
- tiffanyh 4y agoWhere do you see in the article information about 13% IPC improvement at fixed 4.0Ghz? (Was the article link changed after posting. Others in this thread are referencing other things I also don't see in the article)
- deleted 4y ago[deleted]
- neogodless 4y agoThere was a thread last night based on the Anandtech coverage of their launch presentation, which includes the slides they used in the presentation. Here's a direct link to the relevant slide: https://images.anandtech.com/doci/17552/Ryzen%207000%20Tech%20Day%20-%20Keynote%2026.jpeg https://images.anandtech.com/doci/17552/Ryzen%207000%20Tech%...
- slavik81 4y agoThe launch presentation itself is also on YouTube. You can hear it straight from Mark Papermaster, if you like. https://youtu.be/WcH_7xsYtUk?t=11m5s https://youtu.be/WcH_7xsYtUk?t=11m5s
- cillian64 4y agoIPC means “instructions per cycle”, not “instructions per core”. So the numbers you quote would mean a 0% IPC increase (or slight decrease)
- neogodless 4y agoThe numbers quoted have an implicit assumption that performance claims are based on "base clocks", which is incorrect.
- mccorrinall 4y agoYou compare instructions per clock with the clockspeed.
- nazgulnarsil 4y ago... you seem pretty confused by words. Micro architecture is where you get IPC improvements, along with some fraction of the speed and energy efficiency improvements (it's not 100% the node, or rather, designing for a node is in feedback with microarch).
- deleted 4y ago[deleted]
- willis936 4y agoA practical reason for downvotes: having misinformation being the top comment isn't conducive for anything good.
- asdgasfgnuio 4y agoBase clocks are largely irrelevant. These things will run way above or way above that clock speed when appropriate. Furthermore, architecture determines what frequency can be achieved. Designers can choose to sacrifice IPC to increase frequency, or vice-versa. We could build a machine with ridiculously high IPC if you don't mind it running at 1 MHz.
- Symmetry 4y agoYes. You'll essentially never see a 10% clockspeed boost result in 10% faster completion of a benchmark more sophisticated than dhrystone, because you're still limited by the speed of your memory.
- ajross 4y agoIt really depends on the benchmark. Lots of real-world tasks remain highly cache-bound. One important one for me personally is building software. I run big system builds for Zephyr test suites and Chromeos regularly on 64 core devices, and have access to systems with both 4-channel and 8-channel DRAM setups. The doubled memory bandwidth makes for only about 5% higher build throughput. Honestly I think a lot of modern benchmarkery has ended up too far down the "cover all the use cases" rabbit holes, and there's not enough coverage of the kind of boring scalar workloads that most of these systems are being purchased to run.