There are tradeoffs there. Bigger caches mean larger areas, which means longer wires and more complicated clocking. The M1 tops out a little over 3 GHz, vs. 5

There are tradeoffs there. Bigger caches mean larger areas, which means longer wires and more complicated clocking. The M1 tops out a little over 3 GHz, vs. 5 GHz for Intel chips and almost 6 for these new Zen 4 parts.[1] Apple then bets that they can make it up with wider execution units, which seems to have worked out for them (it also explains why boring/unoptimized scalar logic in amateur tests aren't meeting the numbers seen from benchmarks and HPC tests). But it's not about "cache" per se, it's a different design. You need to do a lot more than just increase cache area to duplicate Apple's design choices. [1] A big part of that is, of course, the architecture's genesis as a phone processor. Everyone loves to talk about how efficient the M1/2 are, but the truth is the CPU is a comparatively small part of the energy budget on devices with 5-10W displays. If you were designing a priori for a laptop, you wouldn't necessarily be as power-constrained in your design as the M chips.