I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/ https://clash-lang.org/), and there is a very cool-looking RISC-V SoC

I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/ https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion https://github.com/standardsemiconductor/lion.