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How will the gap widen? 8 instruction parallel decoder will give Apple single core performance per watt, but other than that I don't see what Apple does differe

by zekica 4y ago

How will the gap widen? 8 instruction parallel decoder will give Apple single core performance per watt, but other than that I don't see what Apple does differently. M1 Pro 10 core is their best performance-per-watt, and Ryzen 6800U is just 6% behind [0]. Apple will be ahead, but the gap will not widen. [0] https://www.notebookcheck.net/AMD-Ryzen-7-6800U-Efficiency-Review-Zen3-beats-Intel-Alder-Lake.623763.0.html https://www.notebookcheck.net/AMD-Ryzen-7-6800U-Efficiency-R...

ohgodplsno 4y ago
Apple zealots have this hilariously weird obsession with performance per watt. Do not expect them to look at any actual data.
- gumby 4y ago
  Since the company mainly makes portable devices that is probably the company’s obsession too. And it’s increasingly important in the data center. Not an apple zealot by any means, but I think you shouldn’t be so quick to dismiss. For my own part I’m not sure how to measure performance per watt given all the functional units on die.
to11mtm 4y ago
Wellllll... Ryzen is only 6% behind for multi-core PPW, but The M1 appears to still have a huge advantage in single-core PPW. I have a half dozen thoughts on this, but the foremost is; Apple keeping memory on chip, is likely providing a huge memory latency advantage, (1) as well as some power benefits. It would not surprise me if this is a large part of (if not the majority) of the advantage here outside of the bigger decoder. Think about a single threaded vs multithreaded benchmark; In the case of ST, there's only one thread the prefetcher can deal with, that one thread is going to be waiting for data. In the case of MT, there's a much greater likelyhood that you'll have multiple threads making memory requests, and the latency can be amortized by having the threads do other work (i.e. Thread 1 can start working on data it got back while thread 2's request is already in-flight from controller to DRAM.) This is one of those moments I miss David Kanter (RealWorldTech, [0]) doing CPU arch breakdowns. (1) - Back in the day, one of the 'better' things you could do for a SDRAM P3/Athlon/Duron system, especially if you were replacing all modules for an upgrade anyway, was to hunt for CL2 memory. [0] - https://www.realworldtech.com/cpu/ https://www.realworldtech.com/cpu/
- zekica 4y ago
  Exactly - they have on package RAM with 100GB/s and low latency
- kcb 4y ago
  > Apple keeping memory on chip, is likely providing a huge memory latency advantage How? It's the same LPDDR5 everyone else is using and it's on package not on "chip". The trace length has a negligible impact on latency.
  - 0x457 4y ago
    > The trace length has a negligible impact on latency. Uhm, that is not true. If that was true, then your typical motherboard kept slots where they were 10 years ago, but they're getting closer to combat the increase in latency in other places. This is why HEDT motherboards have such layouts. But just getting it close is not enough: M1 has higher memory latency than AMD and Intel SKUs.
- pclmulqdq 4y ago
  Single threaded perf per watt has never been a benchmark anyone cares about. Perf per watt for the whole die is what counts in power-constrained scenarios. One core on even a 4-core Intel chip (the most power hungry beasts around) cannot hit die-level power or thermal limits.

by zekica 4y ago

ohgodplsno 4y ago

Apple zealots have this hilariously weird obsession with performance per watt. Do not expect them to look at any actual data.

gumby 4y ago
Since the company mainly makes portable devices that is probably the company’s obsession too. And it’s increasingly important in the data center. Not an apple zealot by any means, but I think you shouldn’t be so quick to dismiss. For my own part I’m not sure how to measure performance per watt given all the functional units on die.

to11mtm 4y ago

Wellllll... Ryzen is only 6% behind for multi-core PPW, but The M1 appears to still have a huge advantage in single-core PPW. I have a half dozen thoughts on this, but the foremost is; Apple keeping memory on chip, is likely providing a huge memory latency advantage, (1) as well as some power benefits. It would not surprise me if this is a large part of (if not the majority) of the advantage here outside of the bigger decoder. Think about a single threaded vs multithreaded benchmark; In the case of ST, there's only one thread the prefetcher can deal with, that one thread is going to be waiting for data. In the case of MT, there's a much greater likelyhood that you'll have multiple threads making memory requests, and the latency can be amortized by having the threads do other work (i.e. Thread 1 can start working on data it got back while thread 2's request is already in-flight from controller to DRAM.) This is one of those moments I miss David Kanter (RealWorldTech, [0]) doing CPU arch breakdowns. (1) - Back in the day, one of the 'better' things you could do for a SDRAM P3/Athlon/Duron system, especially if you were replacing all modules for an upgrade anyway, was to hunt for CL2 memory. [0] - https://www.realworldtech.com/cpu/ https://www.realworldtech.com/cpu/

zekica 4y ago
Exactly - they have on package RAM with 100GB/s and low latency
kcb 4y ago
> Apple keeping memory on chip, is likely providing a huge memory latency advantage How? It's the same LPDDR5 everyone else is using and it's on package not on "chip". The trace length has a negligible impact on latency.
- 0x457 4y ago
  > The trace length has a negligible impact on latency. Uhm, that is not true. If that was true, then your typical motherboard kept slots where they were 10 years ago, but they're getting closer to combat the increase in latency in other places. This is why HEDT motherboards have such layouts. But just getting it close is not enough: M1 has higher memory latency than AMD and Intel SKUs.
pclmulqdq 4y ago
Single threaded perf per watt has never been a benchmark anyone cares about. Perf per watt for the whole die is what counts in power-constrained scenarios. One core on even a 4-core Intel chip (the most power hungry beasts around) cannot hit die-level power or thermal limits.