The address registers were paired up with the data registers, so modifying A1 would cause an implicit load into X1, for example. A6 and A7 modifications caused

The address registers were paired up with the data registers, so modifying A1 would cause an implicit load into X1, for example. A6 and A7 modifications caused implicit stores from X6/X7. So with careful register assignment and some offset initialization of address registers beforehand, array processing loops could be encoded in remarkably few instructions.