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I was trying to say that if CISC-to-RISK overhead is the main contributing factor then other laptops without the overhead would be competitive. ThinkPad X13s w
by 3pm 4y ago
I was trying to say that if CISC-to-RISK overhead is the main contributing factor then other laptops without the overhead would be competitive. ThinkPad X13s with a 4 Core Snapdragon for example. It is a pure-RISK machine and it seem to under perform Intel and is almost twice as slow as M1.
- mnw21cam 4y agoRISC is the secret sauce that allows M2 to decode four instructions per clock cycle, due to the constant instruction length, and that is what gives the M2 a speed advantage over CISC instruction sets. The snapdragon CPUs aren't trying to decode four instructions per clock cycle, so they aren't taking advantage of that feature of RISC instructions.
- 3pm 4y agoGot it. It is not enough to have a fixed width instruction set, you also have to actually decode and execute them faster after decoding. Wonder at what point we will start seeing competitive ARM CPUs.