That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it. SPARC had different memory models at

That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it. SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example. RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion https://github.com/standardsemiconductor/lion, highly recommend!