3 ms·
RISC-V is pretty interesting in this regard; it uses weak memory ordering by default, but a CPU that implements TSO can simply flag Ztso, and I believe that wou
by ColonelPhantom 4y ago
RISC-V is pretty interesting in this regard; it uses weak memory ordering by default, but a CPU that implements TSO can simply flag Ztso, and I believe that would be enough to get x86-like memory semantics.
IIRC, Apple M1 uses a similar technique to make sure Rosetta 2 can run translated x86 code without worrying about the memory model. However, M1's implementation can be switched at runtime, while Ztso is not. On the other hand, Ztso is standardized while M1's TSO is not.
Also, the text for Ztso mentions that SPARC uses TSO, just like x86. ARM however is indeed more relaxed.
- benreesman 4y agoThat’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it. SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example. RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion https://github.com/standardsemiconductor/lion, highly recommend!