They sorta have these things, but no one looks at it. For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have be

They sorta have these things, but no one looks at it. For example the scaling factor from from say 5nm to 3nm for transitory is X. But for SRAM, things have been getting progressively worse so it often X/2. And with caches going up you end up using a process node terrible for sram, but needed for cpu transistors, and it’s a huge waste. You can see why you might use a different process tech for caches, and AMD is clearly going this direction. Anyhow, TMSC 3nm is just a marketing term. On the physics side, it has about 7-8 key differences to previous 5nm. That’s 6-7 too many things for people to care or remember about. Intel used to use a part of the transistor when it takes about scale. But then the geometry of the transistor changed! That number no longer has meaning. And transistor geometry changes over time, and you have multiple to choose from on the same process node. Oops. So… back to marketing terms.