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I'm designing in 5nm right now and every process has multiple standard cell libraries to choose from. There is usually a high performance library and then a hi
by lizknope 4y ago
I'm designing in 5nm right now and every process has multiple standard cell libraries to choose from. There is usually a high performance library and then a high density library with smaller cells. The high density library has smaller transistors but the smaller weaker devices are slower. A single chip though will have a mix of both. The high performance cells would be used in the CPU cores while the slower high density cells are used in blocks that don't need the extra speed. An example is an ethernet PHY where the device on the other end of the cable expects you to run a certain speed.
- deleted 4y ago[deleted]
- frozenport 4y agoDoes this mean you have two clock speeds on the same die?
- wtallis 4y agoEven if all parts of a die use the same transistor library, you'll still usually have lots of different clock domains so that different cores can run at different speeds according to how busy they are. And you'll sometimes have a few cores that have been identified as capable of running one or two speed bins higher than the others, from ordinary variation. But there's probably also an example of some phone chip that has Cortex A53 cores implemented on two different transistor libraries to hit significantly different performance/power points.
- exikyut 4y agoOoohh, "power" and "efficiency" cores!! AnD wItH tHe sAmE nUmBeR oF nAnOmEtErS tOo lol
- tambre 4y agoBasically all SoCs these days have plenty of different clock frequencies for different parts. Number of clock domains can easily be over a hundred.
- keepquestioning 4y agoWhat chip?
- bhouston 4y agoApple VR headset? Like an M3? That is my guess. It isn’t early enough for the iPhone 14 which is being released in about a month.
- klelatti 4y agoIncredibly unlikely that we’d see a current Apple employee comment on their work on an upcoming project on here.
- keepquestioning 4y agoThat's speculation
- exikyut 4y agoHonestly could be anything. 5nm's long tail is surely tiny, but it's surely there; it can't be all smartphone SoCs. For example (just to chuck some more entropy on the pile) googling "tesla 5nm" finds a bit of an indication they're doing things in that space.
- RicoElectrico 4y agoSo pick the smallest device size, still would be more grounded in reality compared to "nanometers". Maybe do it like this: plot nm vs density for "properly" named old nodes and extrapolate further for current nodes.
- exikyut 4y agoApologies for the pedantic question - by "certain speed", are slower high-density cells adequate for an Ethernet PHY's requirements? Completely naive about this level of engineering, but very interested :)
- andy_ppp 4y agoCool! I’d love to hear more about the node design process, it seems as though presumably the blocks of transistors are already combined into chip Lego and each of these uses interference patterns to etch things that are smaller than would be possible otherwise? We must be hitting the theoretical limit in a few generations right?